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MSFF

MSFF. Master/Slave Flip Flops. Q1. Q. D. D Q Gate. D Q Gate. GATE. A Master/Slave Flip Flop (D Type). Gated D latch (master). Gated D latch (slave). Either: The master is loading (the master in on ) or The slave is loading (the slave is on )

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MSFF

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  1. MSFF Master/Slave Flip Flops ECEn 224

  2. Q1 Q D D Q Gate D Q Gate GATE A Master/Slave Flip Flop (D Type) Gated D latch (master) Gated D latch (slave) Either: The master is loading (the master in on) or The slave is loading (the slave is on) But never both at the same time… ECEn 224

  3. Q1 Q D D Q Gate D Q Gate GATE DFF Timing MasterLoads SlaveLoads MasterLoads SlaveLoads MasterLoads SlaveLoads Gate D Q1 Q time ECEn 224

  4. Q1 Q D D Q Gate D Q Gate GATE Output Changes in Response to Falling Clock MasterLoads SlaveLoads MasterLoads SlaveLoads MasterLoads SlaveLoads Gate D Q1 Q time ECEn 224

  5. DFF Detailed Schematic D Q Q’ CLK Master latch (D) Slave latch (SR) Usually call the gate “clock” ECEn 224

  6. D Q A Falling Edge Triggered DFF D Q Q’ CLK Edge-triggered CLK Falling edge triggered ECEn 224

  7. D Q Oscillator (Toggle Circuit) Operation D Q CLK CLK Q time ECEn 224

  8. D Q Rising Edge Triggered DFF Schematic D Q Q’ Edge-triggered CLK CLK Rising edge triggered ECEn 224

  9. D Q Oscillator (Toggle Circuit) Operation D Q CLK CLK Q time ECEn 224

  10. D Flip Flop Transition Table Q+ = D No clock shown since it is edge triggered (assumed) ECEn 224

  11. D Q D Q Falling vs. Rising Edge Triggered Qfall Qrise D CLK CLK CLK D Qfall Qrise ECEn 224

  12. Alternative Flip Flops T JK ECEn 224

  13. T Q Toggle Flip Flop T Q CLK Q Q+ = T’•Q + T•Q’ = T + Clock edge is assumedin this transition table… ECEn 224

  14. T Q D Q Toggle Flip Flop T Q CLK Q Q+ = T’•Q + T•Q’ = T + Q An oscillator with an enableinput (T) T CLK ECEn 224

  15. Toggle Flip Flop Q T CLK ECEn 224

  16. J Q K JK Flip Flop J Q K CLK Kind of a cross betweena SR FF and a T FF Q+ = K’•Q + J•Q’ ECEn 224

  17. JK Flip Flop J Q K CLK ECEn 224

  18. Why Alternative FF’s? • With discrete parts (TTL family) • JK or T FF’s could reduce gate count for the input forming logic • Extensively used • With VLSI IC’s and FPGA’s • JK or T FF’s must be built from DFF+gates • Larger, slower than a DFF • Not used ECEn 224

  19. Flip Flops With Additional Control Inputs ECEn 224

  20. What is this? D Q Q’ ??? CLK ECEn 224

  21. What is this? D Q Q’ Enable CLK A falling edge triggered, D-type FF with enableMaster only loads when CLK = Enable = 1 ECEn 224

  22. What is this? D Q Q’ ??? CLK ECEn 224

  23. What is this? D Q Q’ Set CLK A falling edge triggered, D-type FF with an asynchronous setIf Set=1 then Q→1, regardless of CLK or D ECEn 224

  24. What is this? D Q Q’ ??? CLK ECEn 224

  25. What is this? D Q Q’ Set CLK A falling edge triggered, D-type FF with a synchronous setIf Set=1 then Q→1 on the next falling edge of the clock, regardless of D ECEn 224

  26. Flip Flops With Additional Control Inputs • A variety of FF’s have been made over the years • They contain combinations of these inputs: • Enable/load • Set • Reset/clear • The Set and Reset can be either: • Asynchronous (independent of CLK) • Synchronous (work only on CLK edge) ECEn 224

  27. Flip Flop Timing Characteristics ECEn 224

  28. Clock-to-Q Time (tCLK Q) D Q Q’ CLK tCLK  Q = tNOT + tAND + 2 x tNOR The output does not change instantaneously… ECEn 224

  29. tCLK  Q CLK D Q tCLK  Q time ECEn 224

  30. Setup Time (tsetup) D Q Q’ CLK tsetup = tNOT + tAND + 2 x tNOR The input has to get there early enough to set the master latch beforethe clock turns off… ECEn 224

  31. tsetup tsetup CLK D Q time ECEn 224

  32. Setup Time (tsetup) D Q Q’ Same setup time as before CLK ECEn 224

  33. Setup Time (tsetup) D Q Q’ CLK Clock is delayed through the NOT gate ECEn 224

  34. Rising Edge FF Setup Time (tSETUP) D Falling-edge setup time tsetup-old CLKinv tnot CLK Q Time ECEn 224

  35. Rising Edge FF Setup Time (tSETUP) D tsetup-old CLKinv tsetup tnot CLK Q Time ECEn 224

  36. Falling Edge Hold Time (thold) D Q Q’ CLK thold = 0ns (AND gates turn off immediately) You have to keep the old D value there until the ANDgates are shut off… (but no longer) ECEn 224

  37. Rising Edge Hold Time (thold) D Q Q’ thold = tNOT CLK You have to keep the old D value there until the ANDgates are shut off… ECEn 224

  38. Rising Edge Hold Time (thold) thold = tNOT Clock edge AND gate turns off, D can now change CLK D Q time ECEn 224

  39. Flip Flop Timing thold tsetup CLK D Q tCLK  Q time ECEn 224

  40. D Q D Q Timing of a Synchronous System Input Forming Logic Q D tCYCLE >= tCLKQ + tIFL + tSETUP CLK CLK CLK Q D tCLKQ tIFL tSETUP time ECEn 224

  41. D Q D Q D Q D Q Example of a Synchronous System 4 +1Circuit 4 4 CNT = 0000 0001 0010 0011 0100 … 1111 0000 … CLK One transition per clock edge… ECEn 224

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