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Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors

Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors. Javier de San Pedro , Nikita Nikitin, Jordi Cortadella and Jordi Petit Universitat Politècnica de Catalunya (Barcelona ) Project funded by Intel Corp. Outline. Introduction

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Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors

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  1. Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors Javier de San Pedro, Nikita Nikitin,Jordi Cortadella and Jordi Petit Universitat Politècnica de Catalunya (Barcelona) Project funded by Intel Corp.

  2. Outline • Introduction • Architectural exploration of CMPs • Physical planning • Integration with architectural exploration • Floorplanning and wire planning technology • Results and conclusions

  3. Designing a Chip Multiprocessor DSP CMP Off-ChipMemory Graphics Data Mining ⁞ Bioinformatics • How many cores? • How much L2/L3 on-chip cache? • Interconnect: mesh/ring/bus? • How many memory controllers?

  4. Automated exploration Exploration tool Huge design space: Billions of configurations

  5. Our exploration flow Architecturalconfigurations AnalyticalModeling* Promisingconfigurations Simulation *N. Nikitin et al. "Analytical Performance Modeling of Hierarchical Interconnect Fabrics.“ NOCS 2012

  6. MC Configuration example R C2 C2 C2 NI L2 L2 L2 Bus MC MC L2 L2 L2 L3 C2 C2 C1 - 6x4 mesh, 24 clusters - total 144 cores - 6 cores/cluster - 1 C1, 128K L1, 256K L2 - 5 C2, 64K L1, 96K L2 - 146 Mb total shared L3 Throughput = 85.71 IPC MC

  7. Motivation for physical planning • Block area is used during exploration NSWE C C R L2 L2 • Min area, but … • Unbalanced aspect ratio • L2 not adjacent to cores • Uneven distribution of ring routers r r r r r r L2 L2 C C L3

  8. Abutability in tiled CMPs N E W S

  9. Over-the-cell routing 1000 wires  10 µm 500-1000 wires Core Router Cache Tiled CMPs

  10. Physical planning AnalyticalModeling PhysicalPlanning C C L2 L2 C C R Local IC L2 Simulation L3 R L3 • Estimations: • Area • Wirelength • Routability

  11. Floorplanner • Slicing structures & Simulated Annealing* • Lightweight maze router • Constraints: • Adjacency (Core L2) • Balanced links (rings) • Maximum length for critical nets V 1 3 H H 4 5 V 1 2 3 2 4 5 • D.F. Wong and C.L. Liu, “A New Algorithm for Floorplan Design”DAC 1986, pages 101-107.

  12. Wire planner Top view • SAT-based approach for gridded routing • Grid unit: link width ( 500 - 1000 wires) • Customizable for any type of Boolean-encoded constraints (abutability, 1D/2D routing, …) Cross-sectionview

  13. Filteringfloorplans Arealimit

  14. After physical planning

  15. Conclusions • Physical planning has significant impact during architectural exploration of tiled CMPs • Future work: • New topologies (mesh of rings) • Multi-module memory floorplanning • Regularity and choppability

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