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Murali Vijayaraghavan vmurali@mit MIT Computer Science and Artificial Intelligence Laboratory

A Shared Memory Microblaze Manycore Multiprocessor. Murali Vijayaraghavan vmurali@mit.edu MIT Computer Science and Artificial Intelligence Laboratory RAMP Retreat, UC Berkeley, January 11, 2007. Why? A Hardware Emulator for InfiniCore.

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Murali Vijayaraghavan vmurali@mit MIT Computer Science and Artificial Intelligence Laboratory

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  1. A Shared Memory Microblaze Manycore Multiprocessor Murali Vijayaraghavan vmurali@mit.edu MIT Computer Science and Artificial Intelligence Laboratory RAMP Retreat, UC Berkeley, January 11, 2007

  2. Why? A Hardware Emulator for InfiniCore • InfiniCore is a homogeneous manycore research processor under development at MIT • Designed to support both general-purpose computation and high-performance embedded apps • Lots of small cores on one chip • Target is 1K 64-bit cores at 32nm technology node (2012?) • InfiniCore has completely new software stack (new OS, new parallel virtual machines) => Essential to have fast platform for software development • But also, want to help develop more RAMP infrastructure components in the memory system

  3. Goals for First Version • Design a distributed uncached shared memory system containing Microblaze cores • Microblaze OK to get going and has high density, but will eventually migrate cores to new InfiniCore ISA • An RTL model but timing doesn’t necessarily match target • No support for caches: An on-chip network connecting on-chip scratchpad memories and off-chip DRAM. • Support parallel synchronization primitives. • Map & run MIT bthreads (a stripped down version of pthreads sufficient to run many parallel applications) • Suitable for experiments in embedded manycore application mapping

  4. Caveats • This is very preliminary work • Not everything is worked out • Implements small fraction of Infinicore’s functionality • This is not InfiniCore…

  5. One Tile mblaze core LMB Data Bus LMB Inst Bus To DRAM To Router Memory Interface From DRAM From Router Local Data Scratchpad (in BRAM) Local Inst Scratchpad (in BRAM)

  6. 2-D Array of Tiles on one BEE2 FPGA DRAM Tile DRAM DRAM DRAM

  7. Network • Load-Store network, fixed size (header + 32 bits) messages • Separate Request and Reply networks • Static dimension-ordered routing • Route in one dimension first, then route in the other • Flow control in the routers

  8. Design tools • Xilinx IP cores for Microblaze core • BEE2 DDR2 controller core for DRAM controller • Rest of the code in Bluespec

  9. Current status • Designed Memory interface and Router • Stubs written in Bluespec to encapsulate interfaces • LMB buses • DDR2 controller interfaces • BRAM • Finished interconnecting components

  10. In Progress – Hardware synchronization • Atomic read-modify-write instructions using PUT and GET instructions in Microblaze ISA and design custom FSL core (in bluespec) • Rest of the design is almost the same put Local Memory Interface Remote Memory Interface Atomic operation core (FSL core) mBlaze core get Lock for Read-Modify -Write Memory

  11. Future version plans: Load, store buffers & caches • Interaction of load/stores with synchronization instructions • Fences before atomic memory operation • Caches • Microblaze core’s caches with InfiniCore hardware/software coherence protocol

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