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Prototype of the Global Trigger Processor

Prototype of the Global Trigger Processor. GlueX Collaboration 22 May 2012 Scott Kaneta (skaneta@jlab.org) Fast Electronics Group. Presentation Outline. Level 1 Trigger Architecture Overview GTP Hardware Specification Block Diagram Prototype GTP Prototype Status Trigger Equations.

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Prototype of the Global Trigger Processor

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  1. Prototype of theGlobal Trigger Processor GlueXCollaboration 22 May 2012 Scott Kaneta(skaneta@jlab.org) Fast Electronics Group

  2. Presentation Outline • Level 1 Trigger Architecture Overview • GTP Hardware • Specification • Block Diagram • Prototype • GTP Prototype Status • Trigger Equations

  3. Level 1 Trigger Architecture 10Gbps VXS Global Trigger Crate: • Switch A in Global Trigger Crate • Trigger Distribution not shown SD Energy 10Gbps fiber optics Hit Pattern ST (1) TOF (2) FCAL (11) Tagger (2) BCAL (16) L1 Subsystems (# Crates)

  4. GTP Hardware Specification • AlteraStratix IV GX 180 • Pin compatible expansion up to 530k logic elements ($) • Support for up to 16 VXS payloads • 2x 5-Gbps links per payload • 32 LVPECL trigger/clock outputs to TS • 4 channel full duplex Fiber transceiver • 2 Gb DDR2 Memory • Two independent 1-Gb Interfaces • 512 Mb Flash Memory • 256 Mb dedication for configuration • 256 Mb for code or other • 10/100/1000 Ethernet Interface on Front Panel

  5. GTP Hardware Block Diagram Front Panel VXS Backplane Ethernet DDR2 Memory Ethernet 2 / RJ45 RGMII PHY Stratix IV GX 180 Nios II Soft Processor(s) SSP Data 1 Code Flash Link Up 1 . . . 2 / Multi-Image Configuration Flash Configuration Controller CPLD SSP Data 16 Link Up 16 JTAG Clock, Sync Trig1, Trig2 4 / Fiber Transceiver Legend / 4 High Speed Serial Trigger Out General Purpose 4x Densishield / 32 Configuration

  6. GTP Prototype DDR2 Memory 2x 1-Gb Flash Memory 2x 256-Mb 4 Channel Fiber RJ45 Ethernet Jack Altera FPGA Stratix IV GX 4x 8-Channel LVPECL Trigger/Clock Outputs

  7. Prototype Evaluation Status

  8. Ethernet Testing • ARP and Ping fully verify hardware • VHDL TCP/IP stack • Significant work required for usable interface

  9. GTP Equations • From Dave Doughty’s presentation January 2008 • Z >= TFM*TTOF + EFM*EFCal + RM*((EFCal +1)/(EBCal + 1)) • TTOF - Tracks Forward TOF • EFCal - Energy Forward Calorimeter • EBCal - Energy Barrel Calorimeter • Modified from Ben’s implementation for StratixIV • ~2% of FPGA resources • Looking for feedback regarding equations • User modification of equations • FPGA density • Multiple configurations if necessary

  10. GTP Equation

  11. Trigger Applications • Heavy Photon Search test run • Cluster finding in ECal using CTP • Sliding 3x3 window of crystal energies • Calorimeter • 221 channels • 125 cluster processors

  12. Cluster Finding Algorithm + + + Cluster Energy + + + + +

  13. Cluster Finding Design • Targeted Xilinx Virtex 5 LX110T • Significant timing issues • Design pushes limit of this FPGA • Some features not implemented • Control of the number of crystals per cluster • Scalar reporting

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