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Next/Prev Hop

out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. out Qs. Read all summary cells and state. Determine per output port queue depth. Set per output VC pacing. Send DQ summary cell every period (100usec). p 8.

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Next/Prev Hop

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  1. out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs out Qs Read all summary cells and state Determine per output port queue depth Set per output VC pacing Send DQ summary cell every period (100usec) p8 p8 p8 p8 p0 p0 p0 p0 ... ... ... ... p0 p0 p0 p0 p8 p8 p8 p8 queue queue queue queue ... ... ... ... queue queue queue queue cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr cell hdr DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data DQ data MSR Router: Distributed Queuing wugs 192.168.200.X 192.168.204.X P4 P0 SPC/FPX SPC/FPX Next/Prev Hop Next/Prev Hop DQ DQ 192.168.205.X 192.168.201.X P5 P1 SPC/FPX SPC/FPX Next/Prev Hop Next/Prev Hop DQ DQ 192.168.202.X 192.168.206.X P6 P2 SPC/FPX SPC/FPX Next/Prev Hop Next/Prev Hop DQ DQ 192.168.202.2 192.168.203.X 192.168.207.X P7 P3 SPC/FPX SPC/FPX Next/Prev Hop CP DQ DQ 192.168.203.2

  2. Determining the overall rate Define a low and high threshold for the output side queue. if buf_usage < low overall_rate = 300 else if buf_usage < high overall_rate = 150 else overall_rate = 0 Distributed Queuing - Cell Format • Broadcast DQ summary cells every 100usec: • Src port - originating port • Overall Rate - total aggregate rate (BW) allowed to output port for this port (Src port) • Total queue length - total cells queued for delivery to this port (src port) determined during last interval (Actual Output Port Queue Length) • Queue length to X - number of bytes queued for delivery to output port X 16 0 Cell Header VCI = DQVC Overal rate Src port Total queue length Queue length to 0 Queue length to 1 Queue length to 2 Queue length to 3 Queue length to 4 Queue length to5 Queue length to 6 Queue length to 7 Queue length use units of KB

  3. out Qs wugs 192.168.200.X 192.168.204.X P4 P0 SPC/FPX SPC/FPX Next/Prev Hop Next/Prev Hop IP fwd DQ DQ 192.168.205.X 192.168.201.X P5 P1 SPC/FPX SPC/FPX Next/Prev Hop Next/Prev Hop DQ DQ 192.168.202.X 192.168.206.X P6 P2 SPC/FPX SPC/FPX Next/Prev Hop Next/Prev Hop DQ DQ 192.168.202.2 192.168.203.X 192.168.207.X P7 P3 SPC/FPX SPC/FPX Next/Prev Hop CP IP fwd DQ DQ 192.168.203.2

  4. Perform IP Lookup DestNet = 192.168.202.X Use OputVC = 42 50 42 SPC: Example SPC as Input Port (Port = 3) User Space SW Interrupt HW InterruptforAPIC slow path Receive Packet from Previous Hop on VC = 50 slow path Control IP Lookup Table Maintenance Control Output 1 Prev Hop Output 2 ... APIC IP Lookup Device Specific Processing Output N Basic IP APIC Input 1 Input 2 Packet Sent to output port 2 on VC = 42 Next Hop ... Input N interrupt DistributedQueuing (Set Pacing Values) DQ Callback (rt-clock, 100usec)

  5. Packet from Input Port 3, Send to NextHop on VC = 50 50 43 SPC: Example SPC as Output Port (Port = 2) User Space SW Interrupt HW InterruptforAPIC slow path slow path Control IP Lookup Table Maintenance Control Packet Sent to Next Hop on VC = 50 Output 1 Prev Hop Output 2 ... APIC IP Lookup Device Specific Processing Output N Basic IP APIC Input 1 Input 2 Next Hop ... Packet Arrives from input port 3 on VC = 43 Input N interrupt DistributedQueuing (Set Pacing Values) DQ Callback (rt-clock, 100usec)

  6. Current Switch/MSR Configuration wugs 192.168.204.X P4 acat P0 44 SPC/FPX Next/Prev Hop X 43 47 46 50 45 DQ 192.168.205.X P5 bcat P1 45 SPC/FPX X Next/Prev Hop 44 43 46 50 47 DQ P6 192.168.206.X wcat P2 46 SPC/FPX X Next/Prev Hop 45 44 43 50 47 DQ 192.168.203.X scat 192.168.207.X P7 P3 mcat 43 47 SPC/FPX SPC/FPX Next/Prev Hop 44 CP 46 45 45 46 44 50 50 47 43 DQ DQ

  7. IP fwd Simple Multi-SPC Test wugs 192.168.204.X P4 acat P0 44 SPC/FPX Next/Prev Hop X 43 47 46 50 45 DQ 192.168.205.X P5 bcat P1 45 SPC/FPX X Next/Prev Hop 44 43 46 50 47 DQ P6 192.168.206.X wcat P2 46 SPC/FPX X Next/Prev Hop 45 44 43 50 47 DQ 192.168.200.X scat P7 P3 192.168.207.X mcat 43 47 SPC/FPX SPC/FPX Next/Prev Hop 44 CP 46 45 45 46 44 50 50 47 43 DQ DQ

  8. Multi-SPC Test VC Configuration P0 P4 192.168.204.X acat Test Destination 192.168.200.2 44 SPC/FPX Next/Prev Hop X 43 47 46 46 50 45 DQ Test VCI =201 (2X Multiplier) P5 192.168.205.X bcat P1 45 SPC/FPX X Next/Prev Hop 44 43 46 50 50 40 47 DQ 50 50 50/ 40 fwd P6 P2 192.168.206.X 47 wcat 46 SPC/FPX X Next/Prev Hop 45 44 44 fwd 43 50 47 DQ 192.168.203.X P7 P3 scat 192.168.207.X mcat 43 47 SPC/FPX SPC/FPX Next/Prev Hop 44 CP 46 45 45 46 44 50 50 47 43 DQ DQ

  9. fwd Multi-SPC Test VC Configuration 192.168.204.X P4 acat Test Destination 192.168.200.2 P0 44 SPC/FPX Next/Prev Hop X 43 47 45 46 50 45 50 DQ Test VCI =201 (2X Multiplier) 192.168.205.X P5 bcat P1 44 45 SPC/FPX 50/ 40 X Next/Prev Hop 44 43 46 50 40 47 DQ 50 50 fwd P6 192.168.206.X 47 wcat P2 46 SPC/FPX X Next/Prev Hop 45 44 43 50 47 DQ 192.168.203.X scat 192.168.207.X P7 P3 mcat 43 47 SPC/FPX SPC/FPX Next/Prev Hop 44 CP 46 45 45 46 44 50 50 47 43 DQ DQ

  10. Current Switch/MSR Configuration wugs 192.168.204.X P4 acat P0 44 SPC/FPX Next/Prev Hop X 43 47 46 50 45 DQ 192.168.205.X P5 bcat P1 45 SPC/FPX X Next/Prev Hop 44 43 46 50 47 DQ P6 192.168.206.X wcat P2 46 SPC/FPX X Next/Prev Hop 45 44 43 50 47 DQ 192.168.203.X scat 192.168.207.X P7 P3 mcat 43 47 SPC/FPX SPC/FPX Next/Prev Hop 44 CP 46 45 45 46 44 50 50 47 43 DQ DQ

  11. Issues • Control VCs for the SPC - currently requires two: One AAL5 and one AAL0. • Crashes on the SPC • Seems to be large delay between rx’ing Error interrupt and fielding it • Rx appears to take priority over TX in APIC • Ralph’s design

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