PGT 104 ELEKTRONIK DIGIT

1. PGT 104ELEKTRONIK DIGIT CHAPTER 2 Digital Combinational Logic/Arithmetic Circuits

2. Digital Combinational Logic/Arithmetic Circuits • Arithmetic • Adder/Subtractor • Converters • Decoder/Encoder/Comparator • Multiplexer/ Demultiplexer • Parity Circuits • Generators • Checkers

3. Arithmetic - Binary arithmetic - 2’s complement representation - 2’s complement arithmetic - Hexadecimal arithmetic - BCD arithmetic - Arithmetic circuits - Adder / subtractor - 4-bit full-adder/subtractor ICs

4. Basic Combinational Logic - AND-OR Logic How about the truth table?

5. Basic Combinational Logic - AND-OR-Invert Logic

6. Basic Combinational Logic - Exclusive-OR logic How about XNOR logic?

7. Complements(1) • Allow the representation of negative numbers. • Complements are used in digital computers for simplifying the subtraction operation. • Two types of complement for binary numbers: • One’s complement • Two’s complement • The 1’s complement of a binary number is formed by changing 1’s to 0’s and 0’s to 1’s • Example: • The 1’s complement of 1011000 is 0100111 • The 1’s complement of 0101101 is 1010010

8. Complements(2) • The 2’s complement of a binary number is formed by adding 1 to the 1’s complement. • 2’s complement = (1’s complement) + 1

9. Complements(3) • Alternative method to find 2’s complement: • Start at the right with the LSB and write the bits as they are up to including the first 1. • Do 1’s complements of the remaining bits. • Example: • The 2’s complement of 1101100 is 0010100 • The 2’s complement of 0110111 is 1001001

10. Binary Arithmetic Operations Subtraction • Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed. • Example: 0 0 1 1 1 1 1 0 Borrow X: 229 1 1 1 0 0 1 0 1 Y: - 46 - 0 0 1 0 1 1 1 0 183 1 0 1 1 0 1 1 1

11. Combinational Arithmetic Circuits • Addition: • Half Adder (HA) • Full Adder (FA) • Carry Ripple Adders • Subtraction: • Half Subtractor • Full Subtractor • Borrow Ripple Subtractors • Subtraction using adders

12. X 0 0 1 1 Y 0 1 0 1 S 0 1 1 0 C-out 0 0 0 1 Half Adder Truth Table: Outputs Inputs X Half Adder S C-OUT Y Half Adder • Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit. • This operation is called half addition and the circuit to realize it is called a half adder. • S(X,Y) = S (1,2) • S = X’Y + XY’ • S = X Å Y • C-out(x, y, C-in) = S (3) • C-out = XY X Y Sum S C-out

13. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 C-in 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C-out 0 0 0 1 0 1 1 1 Sum S X X XY XY Inputs Outputs 00 01 11 10 00 01 11 10 C-in C-in 1 1 6 6 0 0 2 2 4 4 0 1 0 1 1 1 3 3 5 5 7 7 1 1 C-in C-in Carry C-out Y Y 1 1 1 1 • S(X,Y, C-in) = S (1,2,4,7) • C-out(x, y, C-in) = S (3,5,6,7) Full Adder(1) • Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit. Full Adder Truth Table S = X’Y’(C-in) + X’Y(C-in)’ + XY’(C-in)’ + XY(C-in) S = X Å Y Å(C-in) C-out = XY + X(C-in) + Y(C-in)

14. X’ X’Y’C-in Y’ C-in X Y X Y X’ Sum S X’YC-in’ Y X Y’ X’ Y C-in’ Full Adder C-out C-in X C-in Y C-in C-in’ C-in’ XY’C-in’ X S Y XYC-in C-in’ X XY Y X XC-in C-out C-in Y YC-in C-in Full Adder(2) Full Adder Circuit Using AND-OR:

15. X Y Sum S X Full Adder C-out C-in Y C-in S X XY Y X XC-in C-out C-in Y YC-in C-in Full Adder(3) Full Adder Circuit Using XOR:

16. n-bit Carry Ripple Adders • An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders. • Each full adder represents a bit position j (from 0 to n-1). • Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. • The output of a full adder at position j is given by: Sj = Xj Å Yj Å Cj Cj+1 = Xj . Yj + Xj. Cj + Y . Cj • In the expression of the sum Cj must be generated by the full adder at the lower position j-1. • The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D • Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay = 2 nD

17. Inputs to be added X3X2X1X0 Y3Y2Y1Y0 4-bit Adder C4 C0 =0 C-in C-out X0 Y0 X2 X1 X3 Y2 Y3 Y1 S3 S2 S1 S0 Full Adder Full Adder Full Adder Full Adder C3 C2 C1 Data inputs to be added C4 C0 =0 C-in C-in C-in C-in C-out C-out C-out C-out Sum Output S0 S1 S2 S3 Sum output 4-bit Carry Ripple Adder Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3 Total Propagation delay = 2 nD = 8D or 8 gate delays

18. Data inputs to be added X (X0 to X15) , Y (Y0-Y15) 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder C12 C8 C4 C16 C0 =0 C-in C-in C-in C-in C-out C-out C-out C-out Sum output S (S0 to S15) Y3Y2Y1Y0 Y3Y2Y1Y0 Y3Y2Y1Y0 Y3Y2Y1Y0 X3X2X1X0 X3X2X1X0 X3X2X1X0 X3X2X1X0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 Larger Adders • Example: 16-bit adder using 4, 4-bit adders • Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position. Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 nD = 4 x8D = 32 D or 32 gate delays

19. Negative Binary Number Representations • Signed-Magnitude Representation: • For an n-bit binary number: Use the first bit (most significant bit, MSB) position to represent the sign where 0 is positive and 1 is negative. Ex: 1 1 1 1 1 1 1 12 = - 12710 • Remaining n-1 bits represent the magnitude which may range from: -2(n-1) + 1 to 2(n-1) – 1 • This scheme has two representations for 0; i.e., both positive and negative 0: for 8 bits: 00000000, 10000000 • Arithmetic under this scheme uses the sign bit to indicate the nature of the operation and the sign of the result, but the sign bit is not used as part of the arithmetic. Magnitude Sign

20. X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B-out 0 1 0 0 Half Subtractor Truth Table: Outputs Inputs X Half Subtractor D B-OUT Y Half Subtractor • Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a difference bit D and a borrow out bit B-out. • This operation is called half subtraction and the circuit to realize it is called a half subtractor. • D(X,Y) = S (1,2) • D = X’Y + XY’ • D = X Å Y • B-out(X, Y) = S (1) • B-out = X’Y X Y Difference D B-out

21. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 B-in 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B-out 0 1 1 1 0 0 0 1 Difference D X X XY XY 00 01 11 10 00 01 11 10 B-in B-in 1 1 6 6 0 0 2 2 4 4 0 1 0 1 1 1 3 3 5 5 7 7 1 1 B-in B-in Y Y Full Subtractor(1) • Subtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit. This is called full subtraction. Full Subtractor Truth Table: Inputs Outputs D = X’Y’(B-in) + X’Y(B-in)’ + XY’(B-in)’ + XY(B-in) D = X Å Y Å(B-in) Borrow B-out 1 1 1 1 B-out = X’Y + X’(B-in) + Y(B-in) • S(X,Y, B-in) = S (1,2,4,7) • B-out(x, y, B-in) = S (1,2,3,7)

22. X’ X’Y’B-in Y’ B-in X Y X’ Difference D X’YB-in’ X Y Y’ X’ Y B-in’ X B-in Y B-in B-in’ B-in’ XY’B-in’ X Y XYB-in B-in’ X Y X’ X’Y Y Full Subtractor B-out B-in X’ X’B-in B-out B-in Y D YB-in B-in Full Subtractor(2) Full Adder Circuit Using AND-OR

23. X Y B-in X Y X’ X’Y Y Full Subtractor B-out B-in X’ X’B-in B-out B-in Y D YB-in B-in Full Subtractor(3) Difference D Full Subtractor Circuit Using XOR

24. n-bit Subtractors An n-bit subtractor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways: • By using n full subtractor and connecting them in series, creating a borrow ripple subtractor: • Each borrow out B-out from a full subtractor at position j is connected to the borrow in B-in of the full subtractor at the higher position j+1. • By using an n-bit adder and n inverters: • Find two’s complement of Y by: • Inverting all the bits of Y using the n inverters. • Adding 1 by setting the carry in of the least significant position to 1 • The original subtraction (X - Y) now becomes an addition of X to two’s complement of Y using the n-bit adder.

25. Inputs X3X2X1X0 Y3Y2Y1Y0 4-bit Subtractor B4 B0 =0 B-in B-out D3 D2 D1 D0 Difference Output D Data inputs to be subtracted X3 Y3 X2 Y2 X1 Y1 X0 Y0 B3 B2 B1 Full Subtractor Full Subtractor Full Subtractor Full Subtractor B4 B0 =0 B-in B-in B-in B-in B-out B-out B-out B-out D3 D2 D1 D0 Difference output D 4-bit Borrow Ripple Subtractor Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3

26. 4-bit Subtractor Using 4-bit Adder Inputs to be subtracted Y3 Y2 Y1 Y0 X3 X2 X1 X0 4-bit Adder C4 C0 = 1 C-out C-in S3 S2 S1 S0 D3 D2 D1 D0 Difference Output

27. 1 1 1 1 0 1 0 1 Full Adder Full Adder Full Adder Full Adder C3 C2 C1 C4 C0 = gnd C-in C-in C-in C-in C-out C-out C-out C-out S0 S2 S1 S3 Sum output Examples: • Add the two 4-bit binary numbers A = 1101 and B = 0111. Then show that the parallel binary adder adds the two numbers correctly. • Use 2’s compliment addition to subtract 12 from 25. Then draw subtraction process by using a binary adder. • Determine the binary output for the parallel binary adder for the inputs shown.

28. Next lecture…. • Converters ~ Comparator~ Decoder~ Encoder~ Code converter