Detectors R&D

1. Detectors R&D D. Peter Siddonsa P. O’Connorb a National Synchrotron Light Source Dept. b Instrumentation Division

2. Outline • Requirements for NSLS-II Detectors • NSLS Detector Experience • Emerging Technologies for Sensor/Electronics Integration • Proposed R&D Plan

3. Goals for NSLS-II Detector Development • A pixel detector with multiple-tau time autocorrelation electronics on each pixel • Dynamics of systems on the atomic scale. • NSLS-II’s quasi-DC brightness will make it an optimal source for this experiment. • Megapixel detector with on-pixel correlators can provide sufficient sampling density to access the sub-microsecond domain. • 3D technology will provide the necessary integration density. • A pixelated detector with on-pixel MCA • Simultaneous spectroscopy/diffraction detector. • Energy and spatial resolution. • X-ray microprobes with microdiffraction and fluorescence analysis on the same sample position with the same detector.

4. NSLS Detectors • A series of detectors for selected SR applications has been developed over the past ~5 years • Key technologies: • Silicon pad and strip detectors (Instrumentation) • CMOS Application Specific ICs (Instrumentation) • Advanced Data Acquisition hardware and software (NSLS) • The highly parallel architectures enabled by these technologies lead to significant performance advantages

5. Rapid XRF Elemental Mapping(BNL/CSIRO collaboration) Si pad sensor (96 elements) Low-noise preamp (32 x 3 chan.) Peak detector- multiplexer Pipelined, parallel processor and digitizer 10mm • Hardware: 32-element detector + 2 ASICs + digitizer/processor board. • Dynamic Analysis real-time deconvolution demonstrated at 108 events/second. • X-ray elemental images of Fiji pyrite collected at NSLS X27A beamline. • 800 x 500 pixels of 10um x 10um, collected in 5 hr. • 20X faster than conventional detector. • Increase to 400 elements + NSLS-II brightness would give additional ×104 gain.

6. Detector for Diffraction Applications • Real-time growth / surface modification • Beamline X21 in-situ growth endstation • Reflectivity / truncation rods / GISAXS • Tests at Cornell • System under construction for X9 undulator/CFN • Inelastic scattering • System under construction for Argonne • Interest from SSRL sensor 640 strips 125um pitch 20 ASICs low-noise preamp + discr. + counter 80 mm

7. Limitations of Wirebonded Interconnection throw excess area (can’t tile) pitch • NSLS-II detectors will require: • larger area (100’s cm2) • finer pixels (< 200mm) • more processing power/pixel (MCA, correlators) • mosaic construction

8. Monolithic Approaches for Sensor/ASIC Integration • Common Technology • sensor in CMOS process (MAPS) • transistor in sensor process (DEPFET, XAMPS) • Charge-Shifting • capture charge in a potential well and physically move it to output port (CCD, CDD) • Physical Connection • bump bonding (PbSn, In) • direct wafer-wafer bonding

9. Bump-bonding: Examples ATLAS Vertex tracker 85M pixels 2 m2 silicon PX detector Swiss Light Source 1M, 200mm2 pixels • large modules possible but: • expensive, esp. for fine-pitch • many post-fab process steps • Pb fluorescence • delamination infrared imager (Raytheon)

10. direct wafer-wafer bonding • Ultimate goal is monolithic integration of any technology • Immediate push in industry is for reducing wireload distribution in digital ICs • Science applications being pursued in optical/IR imaging, HEP tracking • FNAL and KEK have active HEP designs • Processes available at Lincoln Labs, JPL, OKI Semiconductor, IBM

11. 3D CMOS/Photodiode Integration Pixel readout chip for ILC 15mm pixel pitch 106 3D vias; yield 99.999% 104 0.18mm CMOS FETs per pixel 3 transistor levels 11 metal layers In fab (10/1/2006) at Lincoln Labs R. Yarama, Fermilab (FEE 2006) bonded 2 wafer imager stack 1024 x 1024 imager oxide bonded 275°C SOI process thinned to 50mm 8mm pixel pitch 106 3D vias; yield 99.999% 3.8x106 0.35mm CMOS FETs 2nA/cm2 dark current 10 frames/sec V. Sunthuralingam, Lincoln Labs (ISSCC2005)

12. R&D Plan • FY 07-08 • research the available 3D foundry services and the CAD tools required to access them • acquire design capability • 1 foundry run (test vehicle) • FY 09-13 • further technology experiments as needed • design of correlator and MCA chips • other detector hardware (vacuum, cooling, motion control) • design and production of DAQ hardware • control, acquisition, and user interface software

13. Milestones: FY 07-08 • Milestones • FY07 • Identify R&D partner with 3D capability. • Acquire design tools compatible with R&D partner. • Research correlator designs. • Research ADC designs. • FY08 • Design a suitable test device to verify 3D capability • Fabricate test device with R&D partner.