2004 (2004 ITRS Exec. Summary and ORTC”) – it’s all about:

1. 2004 ITRS UpdateORTC OverviewNodes, Chip Size, Transistors, Capacity, $ TrendsAlan Allan/Intel Corp 7/14/04 2004 ITRS Interim Status Review [Presentation Rev Version 5b]

2. 2004(2004 ITRS Exec. Summary and ORTC”) – it’s all about: • Economics + Technology…and • Customers, who Buy • Products (emulated and mapped to chips) which, though the customers don’t know or appreciate it, need Semiconductor: • Nodes • Chip Sizes • Transistors • Capacity • $

3. 90’s 21st Century Technology Economics Semiconductor Industry Semiconductor Industry Clear Both Economics + Technology Hurdles = Growth

4. Global & Regional Political & Macro-Economic Environments …and who BUY, based on varying levels of Purchasing Power, PRODUCTS Electronic End Equipment Semiconductors Customer Demand Semiconductor Equipment Materials Ecosystem or Foodchain? Semiconductor & Equipment Materials Sources: NASA.gov ; SEMI Wanted: CUSTOMERS, who breathe, eat, and live in…..

5. Products(As Defined by NEMI PEGs*) * Product [Need] Emulator Groups

6. Drivers Applications (NEMI) Medical Automotive Office Network Defense Portable SIP/SOC (ITRS) SIP/SOC A4 A3 A2 A1 Architectures Chips /Fabrics (ITRS) MPU Memory DSP AMS Source: ITRS Design TWG Figure 1: Potential mapping approach between NEMI and ITRS roadmaps

7. Nodes

8. Fig 2 Production Ramp-up Model and Technology Node 100M 200K Development Production 10M 20K 1M 2K Alpha Tool Beta Tool Production Tool Volume (Parts/Month) 100K Volume (Wafers/Month) 200 First Two Companies Reaching Production 10K 20 First Conf. Papers 1K 2 0 12 24 -24 -12 Months Source: 2003 ITRS - Exec. Summary Fig 2

9. Technology Nodes: Back to 3-year cycle Near Term Long Term Year of Production 2002 [Actual] 2003 2004 2006 2007 2009 2010 2012 2013 2015 2016 2018 hp90 hp65 hp45 hp32 hp22 hp130 Technology Node [DRAM] (nm) 2-Year Technology Cycle [1998-2002actual] 3-Year Technology Cycle Source: 2003 ITRS - Exec. Summary Table C

10. [DRAM] Company A Company B Company C [DRAM Half-Pitch] 3-year Node-Cycle 2-year Node-Cycle 3-year Node-Cycle 2020 Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q03 ITRS 2003: 2003/100(-110nm?) - 2019/16nm: Average 0.5x/2.5years 03 04

11. 2003 ITRS Renewal ORTC Table Header/”Targets”: 2003 ITRS Technology Node Header (**Unchanged from 2001/2002 ITRS):Near-Term Long Term Notes ---------------------------------- -------------------------------- ----- 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018 hp90 hp65 hp45 hp32 hp22 DRAM Unchanged 100 90 80 70 65 57* 50* 45 35* 32 25* 2218* Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed): Poly Unchanged 107 90 80 70 65 57* 50* 45 35* 32 25* 2218* NEW Logic M1: 120 107 95 85 76 67 60 54 48 42 38 34 30 27 24 21 UNCHANGED: MPU Pr GL: 65 53 45 40 35 32* 28* 25 22 20* 18 16 15* 13 11 10* MPU Ph GL: 45 37 32 28 25 22* 20* 18 16 14* 13 11 10* 9 8 7* * Not visible in 2001 ITRS due to no annual columns between "Near Term" and "Long Term" column ranges. The 2001 ITRS Long Term columns are retained for continuity of technology nodes. ** DRAM Half-Pitch Nodes unchanged, however cell design factor improvement has been significantly delayed in the 2003 ITRS. Node timing is based on original 2001 ITRS glossary definition of 10Ku/mo manufacturing with Production-Capable Equipment and Materials. ***Note: Logic Half-Pitch (HP) was based on Un-contacted Logic Poly HP in 2001 ITRS. In the 2003 ITRS, Logic “Metal 1” (M1) was added and correlated with IC TWG “Local Wiring” Pitch/2 [120nm/2003, plus a 3-year target cycle trend]. ** ***

12. Chip Sizes

14. MPU Chip size (mm2) – Historical Trends vs Unchanged 2001-03 ITRS Model* 1000 800mm2 Litho Field Size 286mm2 2 per Field Size New: 704mm2 Litho Field Size 572mm2 Litho Field Size HP MPU 310mm2 CP MPU 140mm2 100 CP Shrink 70mm2 *1999 Leading-Edge .18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 *1999 Leading- Edge .18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2 * ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016 10 1980 1985 1990 1995 2000 2005 2010 2015 2020

15. Transistors

16. Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls] [Transistors] [1971-2003 (1e3)^(1/16yrs) = 54% Ave CAGR]

17. Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls] ITRS -- Long Term “Moore’s Law” @ 2x/3yrs “Moore’s Law” @ 2x/1.5-2yrs “Moore’s Law” @ 2x/1yr ITRS -- Near Term “Moore’s Law” @ 2x/2yrs Integrated Circuit (IC) … TI & Fairchild ca. 1959 You are Here! Zeta-Xistors (1e21) Exa-Transistors (Et) 1e18 50Pt [Transistors] Peta-Transistors (Pt) 1e15 1946 2000 1949 2003 2006 1952 1955 2009 1958 2012 1961 2015 2018 1964 1967 2021 Tera-Transistors (Tt) 1e12 Giga-Transistors (Gt) 1e09 [1971-2019 (1e3)^(1/16yrs) = 54% Ave CAGR] Mega-Transistors (Mt) 1e06 Kilo-Transistors (Kt) 1e03 Est. from Semico: 1997 Product Transistors (Pt) Discrete 0.0002 Analog 0.130 Other Memory 0.98 Other Logic 1.78 SubTotal: 2.88 SubTotal: 2.88 MCU 0.84 MPR 0.36 DRAM 42.9 Flash 1.71 MPU 0.78 Total: 49.47 Semico (SIA): 1997 Product Units (B) Discrete 197.00 Analog 25.90 Other Memory 3.90 Other Logic 14.80 SubTotal: 241.60 SubTotal: 241.60 MCU 4.20 MPR 1.80 DRAM 3.30 Flash 0.57 MPU 0.26 Total: 251.73 One-a-Transistor (t) 1e00 …In the beginning… Bell Labs ca. 1947

18. Capacity

19. Fig 3 Technology Node Compared to Actual Wafer Production Capacity Technology Node Distribution 10 W.P.C.= Total Worldwide Wafer Production Capacity(Relative Value *) Source: SICAS** W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2003.  The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized. hp720nm >0.7mm hp510nm 1 0.7-0.4mm hp360nm Feature Size (Half Pitch) (mm) Feature Size of Technology <0.4mm <0.4mm 0.4-0.3mm <0.3mm <0.3mm <0.2mm 25% <0.2mm hp255nm 25% <0.16mm 0.1 25 %? SIA/SICAS Data: 1-yr delay from ITRS Timing to 25% of MOS IC Capacity 0.3- 0.2mm 25% 25% hp180nm ITRS Technology Node 0.2- 0.16mm hp180 Actual hp130 Actual hp350 Actual hp250 Actual hp90 hp65 hp127nm 3-Yr 3-Yr 2-Yr 0.01 <0.16mm 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 <0.11um F’cast Source: 2003 ITRS - Exec. Summary Fig 3 Year hp90nm ** Source: Semiconductor Industry Capacity Statistics (SICAS) – collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003

20. All Leading Edge Average LEM, LEL L.Edge Average Other IC Average 1.00 910nm 820nm SICAS Node* >25% of MOS IC Capacity 770nm 690nm 650nm 560nm 460nm 400nm 0.40 290nm 225nm LEM: DRAM Flash LEL: MPU DSP 0.20 360nm 255nm 180nm OLE: Graphics ; Std Cell; PLD; MROM; Chipsets; SRAM; Comm; MCU 140nm 127nm OIC: EPROM; Mass Storage; Gate Arrays; Voice and Other; EEPROM; Std Logic; Analog / Linear 0.10 65 nm 90 nm 45 nm 2001 1994 1995 1996 1997 1999 2000 1998 2002 2003 2003 ITRS hpXX (Actual); PrGl ; PhGL 04 Leading Edge Mfg Roadmap “Node” * SICAS Most Leading Edge Node Range** = 25-30% of MOS IC Area, Actual ** Examples: “180nm” = 0.22u-0.18u-0.15u; “130nm” = 0.15u-0.13u-0.11u; “90nm” = 107nm-90nm-75nm ISMT/IEM [Semico] IC Product Technology Profile

21. $, Gestalt

22. Macro Overview – GWP, Revenue, Capacity Demand Snapshot As of 10/23/02 World Electronics, Semi, Tools, Si Area, #Fabs, Wafer Units vs. GWP ($B) History <- 2000 -> F'cast ‘00 WAS: 1.E+05 2.8% 1.E+04 USA GDP AVE ~3-4% 4.2% 6-8%? 7.5% 1 Tera-Dollar $ 1.E+03 8.26% $ 1.E+02 (Mu/1e4) $ 10% CAGR? 7.5-10%? 1.E+01 2010 2020 $ Bilion Dollars ($B); Silicon Sq.In. (Msi/1e4); #Wafers (w / NPW) 47% 15.5 % 1.E+00 47% 29% 5-8%? 1.E-01 10% 15.5 % 1.E-02 1% 0-1%? 1.E-03 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 1976 1958 1960 1962 1964 1966 1968 1970 1972 1974 2006 Source: VLSIR, April, Sept 2001 Tool Sales ($B) Chip Sales ($B) Electronics Sales ($B) GWP ($B) Silicon Sq. Inches (Msi/1e4) Silicon Wafers (Mu/1e4) Total # Fabs (20Kwspm - #/1e04)

23. [VLSIR ca May’03] Past < -- 2002 ‘02 WAS: [~7.5% CAGR] [~15.5% CAGR]

24. Past   Future Estimate: CAGR ’02-’08 = 5.8% VLSIR History: CAGR ’90-’00 = 6.8% CAGR ’90-’01 = 5.6% 10% CAGR 7% -7.5%CAGR

25. $

26. You Are Here! Analog Wave TV, VCR 3” / 4 ” 5” / 6 ” 200mm 300mm “450mm” “675mm” What Can History Teach Us? 7th Wave? $1T Growing to $1T will require a few more “Waves” of emerging Applications, Economies, and Customers! (and, yes, a couple more wafer generations or equivalent productivity improvements!) 6th Wave? Total Semi Revenue 5th Wave? $0.5T 7.5% 10% Portability & Connectivity Wave Multiple Wireless Devices Fuel Cells, Rich Media Total Semi 2003: $166B Source SIA/WSTS Internet Wave Total Semi Revenue Internet Boom, Cell Phones Digital Content Digital Wave Personal Computing 2020 Source: Semico Research Corp, May’04

27. Summary • ITRS Node timing [DRAM Half-Pitch based] is based on the first two leading-edge companies beginning manufacturing ramp • ITRS Nodes [DRAM Half-Pitch based] are forecast to slow from the present 2-year to a 3-year pace after 2003, and slowing design factors are causing density to double only every technology node • Leading-edge DRAM Product first production start Chip Sizes are targeted to remain flat at about 140mm2 for affordability, but will shrink further in size • To keep chip sizes affordable [ie “flat”], the ITRS target “Moore’s Law” DRAM functionality per chip is slowing from 2x/1.5-2yrs to 2x/2.5-3yrs • Leading-edge volume Capacity Demand, as monitored by SICAS, is on the same 2-year pace as the ITRS nodes, with the 130nm technology range (<150nm to >110nm) reaching >25% of MOS IC capacity in 2003

28. Summary (cont.) • There appears to be no slowing in the overall demand for transistors, which has averaged over 50% compound growth since the 70’s – a pace which increases demand 1000 times every 16 years • To keep the cost per transistor and per bit affordable to end-use applications and consumers, the cost to manufacture transistors inside finished semiconductor devices must decrease at a -29% compound rate • The ITRS targets the affordable cost per function reduction target is based on a historical target of -29%, and if this cost reduction can be maintained as demand for total transistors grows at a 53-55% rate, the revenue of the industry could grow at 7.5-10% per year, reaching $1T by 2019-2025 from the 1999 level of $145B • Of course, growing to $1T will require more emerging “Waves” of demand and a couple more wafer generations or equivalent productivity improvements!