Floorplacement

1. Floorplacement Igor L. Markov

2. Floorplacement (the term was coined by Steve Teig of Simplex/Cadence in 2002)

3. Outline • Introduction • Background • Floorplanning • Standard-cell placement • Tricks & extensions • Netlist pre-processing and process migration • Optimization for timing and power • Unification of placement and floorplanning • Large-scale mixed-size placement • Applications to large-scale floorplanning • Free-shape floorplanning • Summary

4. Traditional VLSI Design Flows Specification Partitioning Logic Design Floorplanning Physical Design Placement Routing Fabrication Compaction Testing

5. Unfortunate Trend: Interconnect Does Not Scale Total dynamic power breakdownfor Intel Centrino(global clock included ) Source: Intel, Feb 2004

6. Modern VLSI Design Flows Specification This Work Floorplacement Physical Synthesis Logic Design Partitioning Physical Design Floorplanning Placement Design For Manufacturing Detail Routing Routing Compaction Fabrication Testing

7. Fixed-Die Layout • 10 years ago placement was done for variable die • Except for FPGAs • Modern ASICs use pre-defined floorplans • Layout area, routing tracks, power lines, etcmay be fixed before placement • Area minimization is irrelevant (area is fixed) • New phenomenon: unroutable placements • New phenomenon: whitespace is known a priori • Row utilization% = density % = 100% - whitespace % • Fixed-die layout is harder than variable-die • Can perform variable die with fixed-die tools,but not vice versa • Tools from Cadence, Synopsys, Mentor, IBM explicitly support fixed-die only

8. Review: Partitioning & Floorplanning • Partitioning • Facilitates a hierarchical design methodology(older placers not scalable) • Floorplanning: seeks non-overlapping locations for hard and soft blocks, shapes for soft blocks • Objectives: minimize area and wirelength • Traditionally assumes “variable-die” (full-chip) layout • Partitioning & Floorplanning allow early estimation of interconnect for logic optimization

9. Block-based Design Std-cell Design Mixed-size Design • Large rectangles can represent • Intellectual Property (IP): hard or soft • Macros, memories, data-paths, analog modules • Modules of unsynthesized logic

10. Placement versus Floorplanning • Mathematically, placement and floorplanning (FP) are the same problem • Seek module locations • Must avoid overlaps between modules • Must observe region constraints • Seek to minimize wirelength (power) • Seek to satisfy delay constraints • Main differences • Scale (number of objects) and algorithms • This work: a unified tool (floorplacer)can dynamically invoke FP or placement

11. Placement vs. Floorplanning

12. Outline • Introduction • Background • Floorplanning: datastructures and algorithms • Standard-cell placement • Tricks & extensions • Netlist pre-processing and process migration • Optimization for timing and power • Unification of placement and floorplanning • Large-scale mixed-size placement • Applications to large-scale floorplanning • Free-shape floorplanning • Summary

13. Slicing vs. Non-slicing Floorplans Non-slicing FP: More general Slicing FP: Simpler

14. Classical Block Packing • Seeks non-overlapping locationsof hard and soft blocks • Objectives: minimize area and/or wirelength • Core area not pre-defined (variable-die layout) • Floorplan representations: • Location-based versus topological • O-Tree, B*-Tree, Sequence Pair, TCG, CBL etc • We use SP, but our methods are generally applicable • Simulated Annealing (SA) used for optimization

15. Sequence Pair (SP) • Proposed by Murata et al. [TCAD ’97] • Two permutations of N blocks capture the geometric relation between each pair of blocks (<…a…b…>,<…a…b…>) a is to the left of b (<…a…b…>,<…b…a…>) a is above b • Horizontal (Vertical) constraint graphs • Edge ab iff a is to the left of b (a is above b) • Given block dimensions and an SP, can find locations • O(n2)-time (faster!) • O(n log(n))-time • O(n log(log(n)))-time Top <ABC, BAC> A Right Left B C Bottom

16. Fixed Outline Floorplanning • Not an area minimization problem • Rather a constraint satisfaction problem • “Classical Floorplanning Considered Harmful” [Kahng, ISPD `00] • First addressed in our work [ICCD`01, TVLSI`03]   y-span x-span

17. Floorplan “Slack” (compatible with many FP representations) F D F D E E C C B <FEDBCA, ABFECD> B A A <FED> is the LCS Left Packing Right Packing x-slack for block A = x(Aright) – x(Aleft) x-Slack Computation

18. Example: A Slack-based Move Block with y-slack=0

19. Fixed-outline FP’er Parquet(based on Simulated Annealing)[Adya&Markov, ICCD 01, TVLSI 03] Restart  current floorplan S.A. y-violation S.A. S.A.  x-violation required outline

20. Outline • Introduction • Background • Floorplanning • Standard-cell placement • Tricks & extensions • Pre-processing and process migration • Optimization for timing and power • Unification of placement and floorplanning • Large-scale mixed-size placement • Applications to large-scale floorplanning • Free-shape floorplanning • Summary

21. Global Placement Techniques • Simulated Annealing • TimberWolf • Dragon (Min-cut + SA) • Min-cutpartitioning (IBM-Cplace, Cadence-Qplace, Capo, Feng Shui) • Multi-level Fiduccia-Mattheyses • Analytical Placement • Force-directed [Cheng & Kuh 84] • PROUD [Tsay & Kuh 88] • GORDIAN and GORDIAN-L [Sigl, Dohl & Johannes 91] • Geometric Partitioning [Vygen 97] • Poisson equation [Eisenmann & Johannes, DAC ‘98] • ACG [Alpert et al, ICCAD 2002]

22. Global Placement by Recursive Min-cut Partitioning • Placers using min-cut bisection: Capo, FengShui, IBM CPlace, Cadence QPlace Placement Bin 2 1 End-case placement by branch-and-bound etc. 3 4

23. Detail: Partitioning One Bin Tentative Cut-line 100% area 50% 50%

24. Detail: Partitioning One Bin Shift cutline to equalize density 60% 40% 50% 50%

25. Detail: Partitioning One Bin Actual cutline 60% 40% 40% 60%

26. Min-cut Placement Can Produce Slicing Floorplans • We are going to usethis effect for floorplanning • Potential reductionsin run-time and wirelength • Recall: traditional floorplannersuse Simulated Annealing Slicing Floorplan!

27. Outline • Introduction • Background • Floorplanning • Standard-cell placement • Tricks & extensions • Netlist pre-processing and process migration • Optimization for timing and power • Unification of placement and floorplanning • Large-scale mixed-size placement • Applications to large-scale floorplanning • Free-shape floorplanning • Summary

28. Whitespace Allocation vs Buffering(72K Cells, 74% WS) Uniform WS WL=15.32e6 Filler Cells/Capo WL=8.76e6 Min-cut/IBM WL=11.43e6 ACG/IBM WL=10.48e6

29. Tethering a Cell to a Location • Idea: soft region constraints • Fake nets contribute to wirelength • Penalty for violating soft region constraints • Tunable parameters • Size of tethering box • Number of cells tethered Fake Pin Fake Net

30. Stable Re-Placement • Start with an initial placement • Tether x% of the cells to the locations specified by initial placement • Add fixed pins and fake nets • Rerun placement • Remove fake pins and nets Tethering offers a tunable amountof freedom for further optimization

31. Controllable Stability of Min-cut Placers Capo (randomized min-cut) Initial 0% tether 5% tether

32. Application 1: Process Migration • Shorter design cycles require IP reuse • # of repeaters is increasing rapidlyin more advanced technology nodes • Wires are not scaling as well as devices • More # of repeaters / logic gate • Different minimum local whitespace requirements for blocks during migration • It is desirable to preserverelative timing characteristics of a design

33. Application 2: Floorplan Reshaping • Floorplans may change due to process migration or due to poor initial estimates • When changing the block shape,a designer may want to maintain the relative timing characteristics of the design

34. Examples: Rescaling and Reshaping

35. Use of Netlist Pre-processing • For a placed netlist • Geometrically rescale all locationsXnew = Xold * Widthnew / WidtholdYnew = Yold * Heightnew / Heightold(resulting locations may not be legal) • Unplace all objects, but tether themto the above “ideal” locations • During reshaping, must re-place I/O pads • Perform placement, record legal locations • Remove fake pins and nets

36. Designs Used for Our Experiments Downloaded from http://www.opencores.org

37. Rescaling Results Placer: Cadence Qplace

38. Reshaping Results Placer: Cadence Qplace

39. Tricks for Performance Optimization • Net-weights, net-bounds etc. extend wirelength-driven design flows to timing-driven design flows • Placement-driven synthesis & re-synthesis • Technology mapping, gate sizing and buffering • Gate replication [Lillis et al, DAC 03 and 04] • DAC 04: “Efficient Timing Closure w/o Timing-driven Placement and Routing”, U. Washington • DAC 04: Performance Optimization in Microarchitectural Floorplanning, GA Tech • DAC 03: Cycle-time Opt. in Floorplanning, UCLA • Extended our software (Parquet)

40. Tricks for Power Optimization • Compute net activity factors • Increase weights of active signal nets • Reduce the clock tree length by placingflip-flops closer together • E.g., in a given placement, cluster FFs,connect FFs in each cluster by fake nets;re-place everything • This may increase length of signal nets

41. Outline • Introduction • Background • Floorplanning • Standard-cell placement • Tricks & extensions • Netlist pre-processing & process migration • Optimization for timing and power • Unification of placement and floorplanning • Large-scale mixed-size placement • Applications to large-scale floorplanning • Free-shape floorplanning • Summary

42. A New Generation of Layout Tools • Place objects of very different sizes & semantics • Standard cells • Hard and soft IP • Macros and datapaths • Registers and unsynthesized logic (modules) • Shape modules • Discrete or variable aspect ratios • Flexible shapes (rectilinear or not) • Optimize very different objectives • Handle differences between logicaland physical hierarchies

43. Why Mixed-size Placement is Difficult • IP reuse, memories etc  large rectangles in layout • Mixed-size placement is at least as hard as • Standard cell placement (many small movable modules) • Floorplanning (large, bulky modules are difficult to pack,especially on a fixed die!) • Typical optimization heuristics are move-based • Each move is “local”, i.e., affects few other objects • However, large modules affect many other modules • Some moves have ripple-effect on small cells • Removing overlaps after global placementis not easy, invalidates top-down estimation

44. Cadence-recommended Mixed-size Placement Flow • QPlace (SEDSM) places large modules first • Designer manually removes overlaps • From now on, modules are considered fixed • QPlace is called to place standard-cells • Otherwise, as our experiments show, • Handling many large cells is not ideal in QPlace

45. Cadence (SEDSM/QPlace) Screenshot(v. 5.1.67 in 2002)

46. Cadence (SEDSM / QPlace) Screenshot (v. 5.4.126 in 2004)

47. Relevant Academic Work : Continuous Optimization • Force directed approaches • [Eisenmann, Johannes, DAC ‘98] : mixed-size • Wires modelled as attractive forces • Overlaps modelled as repelling forces • Are good when there isabundant white-space • Otherwise, designer must remove overlaps

48. Relevant Academic Work : Combinatorial Optimzation • Particularly promisingon constrained designs • [Adya & Markov, ISPD `02]: Min-cut Placement + Floorplanning • [Cong et. al, ASPDAC `03]: Multi-level SA placement • [Adya&Markov, ICCAD `03]:Better whitespace distribution • [Madden et. al, ISPD `04]: Min-cut placement + Post Placement Legalization • This work : Floorplacement

49. Capo+Parquet Flow [Adya & Markov, ISPD ’02] • Proposed pre-processing techniques for solving the mixed-size placement problem • Can be used with standard-cell placers • Main approach: loose integrationof floorplanning and placement • Apparently the first publicationto reliably achieve overlap-free placements

50. Capo+Parquet Flow [Adya & Markov, ISPD ’02] (Outline) • Generate initial placement using a standard-cell placer (pre-processing trick) • Generate a fixed-outline floorplanning instance by “physical clustering” • Remove overlaps and generate valid macro locations using a fixed-outline floorplanner • Place small cells again using standard-cell placer with macros considered fixed