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TID and TS

TID and TS. J. William Gu Data Acquisition. Trigger distribution scheme TID development TID in test setup TS development. Trigger Distribution/Data Readout. TS : Trigger control (physical trigger to physical event), SYNC and Clock generation;

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TID and TS

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  1. TID and TS J. William Gu Data Acquisition Trigger distribution scheme TID development TID in test setup TS development

  2. Trigger Distribution/Data Readout TS: Trigger control (physical trigger to physical event), SYNC and Clock generation; TD: TRG/CLK/SYNC optic fanout, link check TI: trigger distribution, ROC control SD: TRG/CLK/SYNC fan out (VXS P0) TI: trigger distribution and ROC readout control; A low jitter global clock (250MHz): pipeline etc.; SYNC: all the front end crate can be synchronized.

  3. TID Development Prototype: TS, TI, TD or combinations of these individual board functions. This is especially useful for test setups (detail next page) Production: (one PCB, two assembly) Dedicated TI (one optic transceiver) Dedicated TD (does not drive P0) Legacy compatibility: With a Mezz card, the TID/TI can behave like an TI_rev2 board, which can connect to TS_Rev2

  4. TID used in test setup TI TI_MASTER TI With TIDs, a system with up to nine crates can be setup. A two-crate system was tested extensively; Limitation: “TS” trigger inputs: 6 (current firmware); 7 with firmware update;

  5. TS development 6 x 4 LEDs board status VME64x VMEJTAG (PROM loading) External Trigger IN Two 15-bit or Four 7-bit source synced VXS TRG/CLOCK/SYNC (pulse mode or serialized mode) TS clock output, or QSFP (driving TI) TS clock input, or QSFP (driving TI) Optional: Trigger to TD, Busy from TD 10 single-ended outputs GTP trigger IN Two 15-bit, or four 7-bit source synced 12 diff. outputs 16 diff. inputs

  6. TS development Trigger: It can accepts up to 30 GTP inputs (from VME P2 backplane) , 30 external inputs (from front panel), and another 15 front panel inputs. It can also generate readout triggers from VME command. (>=) 10-bit trigger (event) types are supported. Every trigger input can be enabled, pre-scaled, and monitored by scalars. Clock: the onboard 250 MHz oscillator, or external input Sync: With the fiber latency measurement (by TI), all the front end crate can be synced to within 4ns (one 250 MHz clock cycle). Backpressure(or DAQ flow control): with BUSY feedback, and status link (opposite link from the TRIGGER word), the DAQ can work in blocking mode, single event locking mode, or free running mode.

  7. TS Development-- Trigger (event) Type lookup table scheme 15x8 15 8 GTP Trigger 16x11 6 5 15x8 15 8 Trigger (event)Type 15x11 15x8 MUX (with priorities) 15 8 >10 External Trigger 5 16x11 15x11 6 15x8 15 8 VME triggers Front Panel trigger 15x8 4 15 4 M-bit input, N-bit output memory lookup table. The table is downloaded by software at startup MxN

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