מבנה מחשב

1. מבנה מחשב תרגול 3

2. Boolean AND Operation Truth Table Equivalent Gate Different notations:

3. Boolean OR Operation Truth Table Equivalent Gate Different notations:

4. Boolean NOT Operation Truth Table Equivalent Gate Different notations:

5. Boolean NAND Operation Equivalent Gate Truth Table

6. Boolean NOR Operation Equivalent Gate Truth Table

7. Boolean XOR Operation Truth Table Equivalent Gate Different notations:

8. How to implement XOR? Which is Better?

9. Boolean Equalities (1) • Rules of Associativity, Commutation. • Other rules:

10. Boolean Equalities (2) • Distribution • deMorgan

11. Example (1):Simplify the expression Compare number of gates

12. Example (2):Simplify the expression

13. 1 1 Evaluating an Expression (1) • Let’s look at the first expression: 1 1 1

14. 1 1 1 Evaluating an Expression (2) • Let’s look at the first expression: 1 =1

15. We get Different Notation for Truth Table 0 0 0 0 1 0 1 0 1 1 1 2 0 0 0 3 1 1 0 0 1 4 0 1 0 1 1 0 1 5 1 6 1 0 0 1 7 1 1 1

16. Disjunctive Normal Form 0 0 0 0 1 It’s easy to transform a DNF formula to its equivalent gates’ representation 0 1 0 1 1 1 4 0 1 0 1 1 0 1 5 1 1 7 1 1

17. Disjunctive Normal Form

18. Flip-Flops • What happens if we create a circle in the logic gates diagram? • Consider the following diagram: This is a S-R Flip-Flop

19. S-R Flip-Flop • S-R Flip Flop truth table:

20. S-R Flip-Flop With a Clock • The CPU is timed by the pulses of a clock. • Maintaining the FF contents when the clock is between pulses (i.e. outputting 0)using the S-R FF:

21. D-Flip-Flop (1) • On each clock pulse the FF should be meaningful • Therefore the R and S lines should be opposite • If so do we still need both of them?

22. D Flip-Flop (2) • D Flip-Flop when the clock is pulsing:

23. Q Q Q D D Latch D D Latch D Clock Q C C Edge Triggered "D" flip-flop The first latch is called the master, the second latch is called the slave • When the clock goes high, the first D latch (master) accepts the change in input • Because of the inverter, the change is blocked from moving on the second D latch (slave). • When the clock goes low, the slave latch accepts the change in input

24. New Components • Two major components of combinational logic are – multiplexors & decoders. • 2-input multiplexor (or selector) is implemented with gates below a b a b c c s s gate implementation symbol

25. c Multiplexors (MUXes) s 0 1 2 3 4 5 6 7 • Multiplexors can have any number of inputs (in theory) • Multiplexors can apply to buses  multiplied for many lines. • Example: 1 x 2 multiplexor on 32 bits bus. a31 b31 M c31 a30 b30 3 X 8 multiplexor c30 M s2 s1 s0 . . . . . . 32 a b 32 c a0 b0 M c0 32 symbol s

26. 0 1 2 3 4 5 6 7 0 1 2 DECODER Decoders 3 X 8 Decoder Each combination of the inputs enables exactly one output

27. Q0 Q1 Q2 Q(n-1) Q Q Q Q ET-D Latch ET-D Latch ET-D Latch ET-D Latch D D D D . . . C C C C Clock D0 D1 D2 D(n-1) Registers Registers can be built from a series of ET D latches connected to the same clock

28. Register File 5 bits read reg 1 read reg 2 Implementation of double read port 32 bits MUX register 0 data 1 data 2 5 bits 32 bits 32 bits read data 1 read data 2 read reg 1 read reg 2 write reg write data register 1 32 bits 32 bits . . . 5 bits 32 bits register 30 5 bits 32 bits 32 bits register 31 32 bits 5 bits write enable MUX 1 bit 32 bits

29. Write Port Implementation write enable 1 bit 1 bit 1 bit n-to-1 decoder register 0 0 1 . . 30 31 C D Clock register 1 . . . 5 bits C D Reg # . . . C D C D register 30 register 31 C D write data 32 bits