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R&D work at SMU

This OptoElectronics Working Group meeting discusses the goals of testing the GOL chip, including clock jitter tolerance, jitter conversion, GOL driving characteristics, irradiation testing, and power-up schemes. The current status and plan of the project are also addressed, along with the mission statement to develop the LOC chip for ATLAS LAr and ID readout upgrades using the promising SOS technology.

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R&D work at SMU

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  1. R&D work at SMU Link-on-Chip development based on the SoS technology, -- see Ping’s talk. System test on the GOL chip. OptoElectronics Working group meeting

  2. The Goals of testing the GOL • The system’s clock jitter tolerance with HDMP-1024 or TLK2501 as the receiver chip. • The jitter conversion from the reference clock to the serial data stream through the GOL. • the GOL driving characteristics with a VCSEL laser as well as DFB and FP lasers. • Irradiation of GOL to probe its limit or reach ATLAS ID upgrade requirement (100 Mrad). • Power-up schemes with CRT4T. OptoElectronics Working group meeting

  3. Boards and system The test setup The GOL testing board Data pattern generation and error detection with LVDS drivers and receivers TLK interface board, to provide LVDS I/O Multi-channel power board with current monitoring OptoElectronics Working group meeting

  4. Current status and the plan • System debugging is close to completion. • BER test done with simple counter data, not PRBS data. • Tests on GOL will follow. • Irradiation test is aimed to be in the fall, need to wait for SOS test chip setup in order to share beam time. Optical eye-diagrams with GOL sending “alignment signals” OptoElectronics Working group meeting

  5. “Mission Statement” • Trying to identify an ASIC technology (SOS) that is • Rad-hard in both TID and SEU effects. This needs to be checked, but look promising from other people’s studies in the past. • Commercially available, easy to work with (design kit, support, etc), suitable for designs with mixed signals (low noise, small cross talk, etc). • Low power, fast. • Economical (or not too expensive). • Develop the LOC chip for ATLAS LAr, and maybe ID, and other sub system readout upgrades. • We welcome collaboration on the SOS technology evaluation and LOC development. (CERN decides to go with IBM 0.13 micron.) • System level study on the GOL chip for possible use in the ATLAS ID readout upgrade, at least gain experience in GHz range optical data link system design for this upgrade. OptoElectronics Working group meeting

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