Digitaals üsteemide verifitseerimine

1. Digitaalsüsteemide verifitseerimine Arvutitehnika erikursus II, IAY0110, 2,5 AP, A Jaan Raik IT-208, 620 2252, 55 13141 jaan@pld.ttu.ee Tallinn University of Technology, Department of Computer Engineering, November 2006

2. Digitaalsüsteemide verifitseerimine Õppematerjal: Hardware Design Verification: Simulation and Formal Method-Based Approaches William K. Lam, Sun Microsystems ............................................... Publisher: Prentice Hall PTR Pub Date: March 03, 2005 ISBN: 0-13-143347-4 Pages: 624 Tallinn University of Technology, Department of Computer Engineering, November 2006

3. Digitaalsüsteemide verifitseerimine 1. Sissejuhatus, verifitseerimise meetodid.(1.1-1.5) 2. Otsustudiagrammid ja ekvivalentsus. (8.1) 3. SAT, sümbolsimuleerimine. (8.4-8.5) 4. Väited ja SystemVerilog Assertions (5.4-5.5) 5. Verifitseerimise kattemõõdud (5.6) 6. Mudelikontroll (9) 7. DECIDER: mudelikontroll ja kattegeneraator 8. Verifitseerimine ja HDL (1.6, 2-4) Tallinn University of Technology, Department of Computer Engineering, November 2006

4. DECIDER as a model checker Tallinn University of Technology, Department of Computer Engineering, November 2006

5. HLDD Coverage Generation Tallinn University of Technology, Department of Computer Engineering, November 2006

6. Sequential ATPG • No efficient deterministic algorithm known • Limited success with simulation-based methods • Functional fault models too inaccurate • A possible trade-off: hierarchical methods Tallinn University of Technology, Department of Computer Engineering, November 2006

7. Hierarchical methods • Bottom-up approach (Murray, Hayes ITC’88) • tests generated at the lower level will be later assembled at the higher abstraction level • very fast but… • … incompleteness problem: constraints imposed by other modules may prevent test vectors from being assembled • Top-down approach (Lee, Patel TCAD’94) • constraints extracted at the higher level with the goal to be considered when deriving tests for modules at the lower level. Tallinn University of Technology, Department of Computer Engineering, November 2006

8. Recent works including DDs • Assignment Decision Diagrams + SAT (Ghosh, Fujita DAC’00; Zhang et al. ITC’03) • ADD combined with satisfiability methods • High-Level Decision Diagrams (Raik DATE’99) • HLDD based hierarchical ATPG DECIDER • Fault models for FUs and MUXes • Shortcomings: • Mainly FUs targeted, control part ignored... Tallinn University of Technology, Department of Computer Engineering, November 2006

9. HLDD versus ADD • ADDs structure closely matches the RTL design. In HLDDs, a synthesis to extract control relationships has been carried out. • ADD model includes four types of nodes (read, write, operator, assignment decision). In HLDD the nodes are treated uniformly. • ADDs do not support decision-making implicitly • Edges in ADD model have no labels! Tallinn University of Technology, Department of Computer Engineering, November 2006

10. High-level decision diagrams • Register-Transfer level view of a digital circuit Tallinn University of Technology, Department of Computer Engineering, November 2006

11. Decision diagrams for datapath a) Datapath architecture b) Decision diagram Tallinn University of Technology, Department of Computer Engineering, November 2006

12. b) Decision diagram a) FSM state table Decision diagrams for control part Tallinn University of Technology, Department of Computer Engineering, November 2006

13. DECIDER algorithm • General flow Tallinn University of Technology, Department of Computer Engineering, November 2006

14. DECIDER algorithm • High-level test generation constraints Tallinn University of Technology, Department of Computer Engineering, November 2006

15. DECIDER algorithm • Fault manifestation (test setup) Tallinn University of Technology, Department of Computer Engineering, November 2006

16. DECIDER algorithm • Fault effect propagation on HLDDs Tallinn University of Technology, Department of Computer Engineering, November 2006

17. Fault effect propagation. Algorithm graph flow Tallinn University of Technology, Department of Computer Engineering, November 2006

18. DECIDER algorithm • Backtracing (constraint justification) Tallinn University of Technology, Department of Computer Engineering, November 2006

19. Backtrace (justification). Algorithm graph flow Tallinn University of Technology, Department of Computer Engineering, November 2006

20. Extraction of high-level test constraints Tallinn University of Technology, Department of Computer Engineering, November 2006

21. Extraction of high-level test constraints Tallinn University of Technology, Department of Computer Engineering, November 2006

22. DECIDER fault models • Hierarchical fault model for FUs (Raik DATE’99) • Functional fault model for MUX (Raik DDECS’04) • Mixed hierarchical-functional fault model for the conditional operators • The main contribution of this paper • Biggest challenge: there is no path through the datapath for observing conditional modules Tallinn University of Technology, Department of Computer Engineering, November 2006

23. Fault model for conditions • Distinguish correct/faulty values of respective registers • Propagate fault effect to an output • Justify and apply low-level test patterns Tallinn University of Technology, Department of Computer Engineering, November 2006

24. Experimental results Tallinn University of Technology, Department of Computer Engineering, November 2006

25. Experimental results Tallinn University of Technology, Department of Computer Engineering, November 2006

26. Experimental results Tallinn University of Technology, Department of Computer Engineering, November 2006

27. Experimental results Tallinn University of Technology, Department of Computer Engineering, November 2006

28. Conclusions and future work • A new functional fault model for comparison operators proposed and integrated into the DECIDER system • Experiments show that inclusion of the new model increases FC by 0.5-5 % • Additional fault models needed to fully cover faults in FSMs Tallinn University of Technology, Department of Computer Engineering, November 2006

29. VERTIGO plans Tallinn University of Technology, Department of Computer Engineering, November 2006

30. Co-operation • Run Laerte++ and Decider on same bench-marks and investigate the covered fault sets • Pass information from Laerte++ to Decider to target hard faults or check partial solutions • To Do: • interface between the engines (var. names etc.) • a proper constraint solver for Decider • support for new fault models Tallinn University of Technology, Department of Computer Engineering, November 2006