Calc2 Design

1. Calc2 Design • Allows up to 4 incomplete requests on each port • Tag is required to match request to response

2. Calc2 Typical Timing

3. Some Calc2 Test Cases

4. Test Generation Strategies Deterministic vs. random - how tests are generated Pregenerated vs. on-the-fly - when tests are generated

5. Generic Test Generation Algorithm • Describe test generation possibilities as an algorithm • The algorithm will be coded in HVL • Decision points are key

6. Test Generation Alg. for Calc2 Port CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON

7. Deterministic, Pregenerated for Calc2 • Each path through the test gen. Algorithm flow is a test case • Manually select a set of paths in the algorithm, prior to testing • May restrict paths to match test case requirements • Manually generate expected responses CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON

8. Deterministic, On-the-Fly for Calc2 • Manually specify important inputs deterministically • Allow non-important inputs to be filled in randomly during simulation CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON • Must also specify interesting outputs

9. Deterministic, On-the-Fly for Calc2 CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON • Stimulus generation must be intelligent • - force overflow/underflow • - Assign tags to avoid conflicts

10. Role of the Scoreboard Port Number Tag CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON • Contains information on current transactions • - tags, command, inputs, port • - used by checker

11. Pregenerated Random Test Cases • Test cases are not written manually, they are written in a directed random way • Engineer provides atemplate for the test cases and some randomization parameters Port Number Tag CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON

12. Test Case Templates Port Number Tag CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON

13. Randomization Parameters • Production rules are weighted to direct test stimulus generation Port Number Tag CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON

14. Result Checking • Golden Vectors • Output vectors are stored in the scoreboard • Checker compares DUV results to scoreboard data • Cycle-Accurate Reference Model • Reference model reimplements DUV function • Checker compares reference model results to DUV outputs • Transaction Based • Testbench in defined in terms of “transactions” • Scoreboard acts as a reference model, not cycle accurate Port Number Tag CLEAR ALL BUFFERS AND QS Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON

15. On-the-Fly vs. End-of-Test Checking • On-the-Fly • Easy to do using verification languages (assertions, etc.) • Debugging is easier, access to entire state • Lower memory requirements • Probably increases simulation time • End-of-Test • Helpful if signal access is limited • May be performed outside of simulation engine

16. Assertion-Based Result Checking • Assertions act as a substitute for a complete reference model Example: Adder Assertions If the LSBs of the inputs are the same then the LSB of the output is 0. If the sign bits of the inputs are the same then the sign bit of the output is equal to the input sign bits (no overflow) • Assertions catch some errors but not all errors

17. Debugging Bugs can exist in the following places: Design Environment (testbench) Specification Tools • Tool bugs are less likely

18. Debug Process

19. Interactive Debugging Information • Print Statements • May be verbose • May attach to monitors • Assertions • Efficient but may be incomplete • Waveform Viewers • Very verbose but shows timing information • Memory Debuggers • Dump entire state periodically • Verbose but may reveal memory leaks