Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

1. Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing Suraj Sindia (I.I.Sc, Bangalore) Virendra Singh (I.I.Sc, Bangalore) Vishwani D. Agrawal (Auburn University) VDAT 2009

2. Linear Circuits – Quick Recap • Transfer function representation λ<µ VDAT 2009 1

3. Circuit Parameters & Transfer Function Coefficients • f1 and f2 • Maps the parameter space & coefficient space. • Linear functions of circuit parameters • Can be potentially used to track the parametric drifts in circuit parameters c1 c2 f1 R1 R2 C1 C2 f2 Parameter Space Coefficient Space Savir, ITC, 2002 VDAT 2009 2

4. p1 Coefficients as functions of circuit parameters c5 c4 c2 c3 c1 p2 p3 Background of TFC Method VDAT 2009 3

5. Hypercube distribution of ck Legend y = p2 Γk p2n(1+ ρ) Λk Ξk p2n Ω p2n(1- ρ) p1n (1+ρ*)p1n (1-ρ*)p1n x = p1 (1-ρ)p1n (1+ρ)p1n Closer Look at Coefficients 4

6. Defect Level: Probability of a faulty chip escaping as a fault-free or a good chip Probability of a coefficient taking a value in the region Λk Fault Coverage: Percentage of faults that a given test method can uncover from set of all possible faults Probability of a coefficient taking a value in the region Γk Our Work – “Bounding” Hypercube distribution of ck y = p2 Legend Γk p2n(1+ ρ) Λk Ξk p2n Ω p2n(1- ρ) p1n (1+ρ*)p1n (1-ρ*)p1n x = p1 (1-ρ)p1n (1+ρ)p1n VDAT 2009 5

7. Our Work – “Bounding” • Assume an appropriate p.d.f over the region of drift of p1,p2 Є [0,∞] • We choose Gaussian • Relevant for most of passive devices [R,L,C] • Evaluate the joint Gaussian distribution over these regions • Validate the bounds against number of components and coefficient of uncertainty(є) for common circuits – • Eg.: RC Ladder network VDAT 2009 6

8. Equations – Two Parameter Case VDAT 2009 7

9. Closed Form Expressions –N parameters Where, VDAT 2009 8

10. Results – Plots of Expressions DL v/s number of circuit parameters DL v/s є VDAT 2009 9

11. Simulated Plots for RC Ladder Defect Level VDAT 2009 10

12. Simulated Plots for RC Ladder Fault Coverage VDAT 2009 11

13. Simulation-Optimization Tradeoff Tradeoff point VDAT 2009 12

14. CircuitSourceComponent Count Defect Level(%) Transistor Opamp Resistor Capacitor Total(N) Computed Simulated Operational ITC ’97a 8 - 2 1 11 6.51 5.69Amplifier #1 Con. Time State ITC ’97b - 3 7 2 12 5.89 5.23 Variable filter Operational ITC ’97c 10 - - 1 11 6.51 5.69Amplifier #2 Leapfrog Filter ITC ’97d - 6 13 4 23 1.38 1.33 Digital-to-Analog ITC ’97e 16 1 17 1 35 0.21 0.2Converter Differential Amplifier SFAa 4 - 5 - 9 7.72 6.43 Comparator SFAb - 1 3 - 4 7.78 3.75 Single Stage Amplifier SFAc 1 - 5 - 6 8.73 6.17 Elliptical filter SFAd - 3 15 7 25 1.02 0.99 Low-Pass Filter Lucent1 - 1 3 1 5 8.51 5.30 Defect Level on Benchmarks VDAT 2009 13

15. CircuitSourceComponent Count Fault Coverage(%) Transistor Opamp Resistor Capacitor Total(N) Computed Simulated Operational ITC ’97a 8 - 2 1 11 84.78 85.31Amplifier #1 Con. Time State ITC ’97b - 3 7 2 12 87.17 87.66 Variable filter Operational ITC ’97c 10 - - 1 11 84.78 85.31Amplifier #2 Leapfrog Filter ITC ’97d - 6 13 4 23 98.05 98.19 Digital-to-Analog ITC ’97e 16 1 17 1 35 99.75 99.78 Converter Differential Amplifier SFAa 4 - 5 - 9 78.75 79.18 Comparator SFAb - 1 3 - 4 49.57 50.21 Single Stage Amplifier SFAc 1 - 5 - 6 64.19 64.87 Elliptical filter SFAd - 3 15 7 25 98.61 98.72 Low-Pass Filter Lucent1 - 1 3 1 5 57.50 58.18 Fault Coverage on Benchmarks VDAT 2009 14

16. Conclusion • Closed form expressions for bounds on Defect Level and Fault Coverage in TFC based test of analog circuits • Higher component count leads to • Smaller defect level • Better fault coverage • Strategy for opting between simulation and non-linear optimization in TFC based test VDAT 2009 15

17. Thanks for Your Attention!