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Get a summary of the unbiased radiation campaign results on the RD53A chip at room temperature and the preliminary results of the biased campaign at -10°C. Explore the characteristics of the facility and the X-ray machine used for the campaign.
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RD53A un biased radiation campaign results Vasyl Drozd, Jeglot Jimmy, Christophe Sylvia, Maurice Cohen-Solal, Abdenour Lounis, Ennio Monteil, Marco Vogt, Ahmed Abdirashid, Luis Miguel Jara Vasyl Drozd, Luis Miguel Jara Casas 26/06/2018
Outline 0. Summary of the campaign and characteristics of the facility • Results of the 500Mrad, room temperature, unbiased campaign • First preliminary results of the 500Mrad, -10C (approx.), biased campaign
Goal: test the radiation effects on a unbiased RD53A at room temperature, as these are the normal conditions when sensor testing. • 1 chip was irradiated up to 500 Mradat room temperature, unbiased (chip only powered to take measurements pre-irrad, at 150Mrad and at 500Mrad) • After irradiation, the chip was kept with bias at room temperature. • XRAY facility: • Campaign done at CERN ATLAS Pixel group X-Ray machine: https://ade-pixel-group.web.cern.ch/ade-pixel-group/xray/ • Dose rate achievable: 3.9 Mrad/h • Beam is uniform inside an aperture of 37°, chip is placed at a distance of around 10-11 cm, so the whole RD53A chip is covered uniformly. • Cold interface (based in nitrogen flow inside the chamber) can reach -10°C, small drier also available. • Some small issues with the x-ray machine and cooling system during the irradiation, constant monitoring is needed. Cold interface 0. Summary of the campaign and characteristics of the facility:
Test system used: • BDAQ53, version 0.6.0. • KC705 with DP to SMA PCB adapter • 1.28Gb/s output • SCC configuration: • STATUS jumper connected • R3=5k • LDO mode used when taking measurements, analog Vref forced externally to increase Vdda. • Power and temperature conditions: 1. Results of the 500Mrad, room temperature, unbiased campaign Pre-irradiation: VDDA = 1.195V VDDD = 1.18 V T = 37.8C 150 Mrad: VDDA = 1.193V VDDD = 1.17 V T = 35.8C 500 Mrad: VDDA = 1.30V VDDD = 1.19 V T = 34.5C Annealing: VDDA = 1.30V VDDD = 1.17 V T = 35.6C • After 500Mrad, VDDA was needed to be increased to make the PLL lock • It was needed to keep VDDA at around 1.3V during annealing. If reduced, PLL fails.
Also some configuration issues were seen during annealing: • Sometimes when writing the configuration, it kept as in its previous state. • This was detected when testing the ring oscillators, when we saw the same number of counts in their counters for different lengths of the global pulse. • Each ring oscillator drives a 12-bit counter, that counts the number of pulses of the ring while the Start/Stop (Global pulse) signal is high. This was solved writing the configuration recursively until success. 0. Results of the 500Mrad, room temperature, unbiased campaign Example: normal operation: Example: failure: Global pulse = 102.4 ns ; COUNTS =44 Global pulse = 102.4 ns ; COUNTS = 44 Global pulse = 3276.8 ns ; COUNTS = 1371 Global pulse = 3276.8ns ; COUNTS = 44!!
In general, no issues with the digital scans. • Some punctual different results in next slide. Pre-irradiation: 150Mrad: 500Mrad: • Results: digital scans: RD53 internal RD53 internal RD53 internal 1 days annealing room T: 7 days annealing room T: 15 days annealing room T: RD53 internal RD53 internal RD53 internal
7 days, annealing room T: 7 days, annealing room T: • In general, no issues with the digital scans. • Some punctual different results in next slide. RD53 internal • These are just punctual scans, most of the times we got good digital scans. • Repeating the scans or power cycling or powering off the chip for a while, they recover the normal operation. 15 days, annealing room T: 15 days, annealing room T: 9days, annealing room T: • Results: digital scans: RD53 internal RD53 internal 15 days, annealing room T: 15 days, annealing room T: 7 days, annealing room T: RD53 internal RD53 internal RD53 internal
500Mrad: 150Mrad: Pre-irradiation: Some noisy pixels, VTH_SYNC increased to 250 for analog scans VTH_SYNC = 130 VTH_SYNC = 250 • Results: sync FE: Wait-cycles = 10 Width = 9 VBL_SYNC = 400 VBL=Baseline voltage for offset compensation Here we didn’t try too many parameter combinations to reduce impact of annealing. Wait-cycles = 10 Width = 9 VBL_SYNC = 370
500Mrad: 150Mrad: Pre-irradiation: Some noisy pixels, VTH_SYNC increased to 250 VTH_SYNC = 130 VTH_SYNC = 250 • Results: sync FE: Wait-cycles = 10 Width = 9 VBL_SYNC = 370 Here we didn’t try too many parameter combinations to reduce impact of annealing. Wait-cycles = 10 Width = 9 VBL_SYNC = 370 Wait-cycles = 10 Width = 9 VBL_SYNC = 400
500Mrad: Wait-cycles = 10 Width = 9 VBL_SYNC = 370 Keeping same parameters during annealing: • Results: sync FE: 9days, annealing room T: 1 day annealing room T: 2 days annealing room T:
500Mrad: 150Mrad: Pre-irradiation: Vthreshold_LIN = 400 Vthreshold_LIN = 400 Vthreshold_LIN = 400 • Results: linear FE: after tuning:
500Mrad: 150Mrad: Pre-irradiation: Vthreshold_LIN = 400 Vthreshold_LIN = 400 Vthreshold_LIN = 400 • Results: linear FE: 500Mrad:
500Mrad: Keeping same parameters during annealing, after tuning: • Results: linear FE: 9days, annealing room T: 1 day annealing room T: 2 days annealing room T:
500Mrad: 150Mrad: Pre-irradiation: VTH1_DIFF = 4 VTH1_DIFF = 0 VTH1_DIFF = 4 VTH1_DIFF = 0 VTH1_DIFF = 4 VTH1_DIFF = 0 • Results: Differential FE: 9days, annealing room T: 1 day annealing room T: 2 days annealing room T:
Test system used: • BDAQ53, version 0.6.0. development and CDR/PLL bypass mode available • KC705 with DP to SMA PCB adapter • 1.28Gb/s output • SCC configuration: • STATUS jumper connected • R3=5k • Direct powering mode used 2. Results of the 500Mrad, -10C, biased • After 200Mrad, VDDA was needed to be increased to make the PLL lock, Vdda to 1.3V • The chip has been kept in the xray cabinet for some days, cold: • With last chip, when warming it up, some of the wire bonds broke, possibly due to the drier (not optimal). • We have kept the chip inside for some days to take some measurements before taking it out of the xray, so in case the same issue happens during the warming up we have some data after irradiation. • Ring oscillators do not show much recovery after irradiation when kept it cold.
In general, no issues with the digital scans. • Some punctual different results in next slide. Pre-irradiation: 300Mrad: 500Mrad: 2. Results: digital scans: RD53 internal RD53 internal RD53 internal 1day after irradiation, cold: 2days after irradiation, cold: RD53 internal RD53 internal
350 Mradcold, biased:(quick measurements done during irradiation, results can be improved): Sync FE, 350Mrad Lin FE, 350Mrad Diff FE, 350Mrad RD53 internal RD53 internal RD53 internal RD53 internal RD53 internal RD53 internal Different Scales!! Different Vths!!
500Mradcold, biased: Sync FE, 500Mrad Lin FE, 500Mrad Diff FE, 500Mrad RD53 internal RD53 internal RD53 internal Different Scales!! Different Vths!!
Ring oscillators: 500Mrad, T=-7.79C Vddd = 1.14V 2 days annealing cold: T=-7.06C Vddd = 1.15V Before irradiation: T=-7.06C Vddd= 1.17V RD53 internal RD53 internal RD53 internal Frequency decrease: about 20-25%
We have just moved the chip to our climatic chamber, where we can do more detailed measurements. • More results will be shown in next meetings. 2. Next/current plans: