ECE 463/521 Fall `18

1. ECE 463/521Fall `18 Basic Cache Operation Prof. Eric Rotenberg ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

2. MAIN MEMORY 32-bit address 1 byte of data 232 bytes ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

3. block address block offset 1 block = 8 bytes MAIN MEMORY 32-bit address 001 010 011 100 101 110 111 000 • Block offset • Low-order bits of address that specify a byte within the block • Since cache is managed at granularity of blocks, the block offset bits are irrelevant for determining hit or miss 232 bytes (229 memory blocks) ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

4. 1 block = 8 bytes MAIN MEMORY CACHE 32-bit address block address block offset • Example: • SIZE = 32 bytes • BLOCKSIZE = 8 bytes • 1 block per cache set 001 010 011 100 101 110 111 000 ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

5. index 1 block = 8 bytes MAIN MEMORY CACHE 32-bit address blockaddress block offset 001 010 011 100 101 110 111 000 • Index • Low-order bits of block address indicate which cache set the block will be placed in and where it will be searched for later ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

6. tag data v 1 block = 8 bytes MAIN MEMORY CACHE 32-bit address block address block offset 001 010 011 100 101 110 111 000 index tag • Tag • Many memory blocks have the same index, i.e., they map to the same cache set • High-order bits of block address differentiate memory blocks that map to the same cache set • Record the tag alongside the cached memory block, to identify which memory block is cached in the set ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

7. Cache design considerations • Block size • What is the atomic unit of storage in the cache? • Block placement • Where can a block be placed in the cache? • Block identification • How is the block found in the cache? • Block replacement • Which block should be replaced on a miss? • Write strategy • What happens on a write? ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

8. Block size • Typical values for L1 cache: 16 to 64 bytes • Exploit spatial locality: • Bring in larger blocks • Slows down time it takes to fix a miss (“miss penalty”) • Too large and “hog” storage (“cache pollution”) 32-bit address 31 b b-1 0 block address block offset # block offset bits = log2(Block Size) ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

9. A direct-mapped cache 31 6 5 3 2 0 MAR tag index block offset (3) (26) (3) set (holds 1 block) tag (26 bits) blocks (8 bytes) TAG STORE DATA STORE row dec LATCH LATCH =? word select (mux) MDR hit/miss ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

10. A (2-way) set-associative cache 31 5 4 3 2 0 MAR (2) (3) tag index block offset (27) set (holds 2 blocks) tag (27 bits) blocks (8 bytes) row dec =? =? block select (mux) Notes: this cache is the same size as the (previous) direct-mapped cache, but the index field is 1 bit shorter (2 bits total) A direct-mapped cache is really a 1-way set-associative cache word select (mux) MDR ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

11. =? =? =? =? =? =? =? =? tag tag tag tag tag tag tag tag A fully-associative cache(also called a content addressable memory or CAM) 31 3 2 0 MAR tag block offset (3) (29) tag (29 bits) Notes: Same size as previous caches, but no row decoder and no index at all! Comparators (one per block) take the place of the row decoder word select (mux) MDR ECE 463/563, Microprocessor Architecture, Prof. Rotenberg

12. Summary: decoding the address • Cache is normally specified as follows: • {SIZE, ASSOC, BLOCKSIZE} • SIZE: total bytes of data storage • ASSOC: associativity (# of blocks in a set) • BLOCKSIZE: size of cache block in bytes • Question: how do we decode the address? • REMEMBER the following equation • Then compute size of each address field tag index block offset ? ? ? tag index block offset ECE 463/563, Microprocessor Architecture, Prof. Rotenberg