University of Rostock, Germany Institute of Mathematics

1. Algorithms for Leakage Reduction with Dual Threshold Design Techniques Konrad Engel, Thomas Kalinowski, Roger Labahn, Frank Sill, Dirk Timmermann Institute of Mathematics, Institute of AMCEUniversity of Rostock SoC‘06 International Symposium on System-on-Chip Dual Threshold Voltages DTCMOS Measured at NAND2 BPTM 65nm Technology New Algorithms • Definitions • LVT version of vertex v • => Delay: d0(v) Leakage: c0(v) • HVT version of vertex v • => Delay: d1(v) Leakage: c1(v) • d0(v) < d1(v), c0(v) > c1(v) • cost function of realization (G,x)(x:V→{0,1}): • length of a path P = (v0,,…,vk) inside (G,x): • slack(v,x): how much can v be delayed without effects on evaluation time of (G,x) • set of candidates vertices • dif(v) = d1(v) – d0(v), c(v) = c0(v) – c1(v) • DTCMOS: find decision function such that • d(G,x) = dmin(G,x), c(G,x) is minimal • Single and the Multiple Switch Algorithms • (SSA and MSA) • start with LVT version of (G,x0):x0(v) = 0 for all v • each optimization step: • weight(v) = slack(v,x) – dif(v) + λc(v) • SSA: vertex with highest weight switched to HVT • MSA: more vertices are switched to HVT • until there are no more candidate vertices • k-Family Algorithm (k-FA) • k-Cutset Algorithm (k-CA) • switch the whole candidate set to HVT • put , switch vertices in minimum weighted k-cutset in Gxto zero and iterate this until dmin(G) is reached • continue until the candidate set is empty Simulation Results [1] F. Sill et.al., “Low Power Gate-level Design with Mixed-Vth (MVT) Techniques“,17th SBCCI, 2004. University of Rostock, Germany Institute of Mathematics Institute of Applied Microelectronics and Computer Engineering Contact: konrad.engel@uni-rostock.de, frank.sill@uni-rostock.de