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Intel 8086

Intel 8086. Registers. (16-bit) registers: Data reg. – to hold data for an op. Address reg – to hold addr of an instruction or data Status reg / FLAGS reg. 1. Data reg - 4. AX BX CX DX High byte – H Low byte – L AX  AH + AL. AX – Accumulator reg.

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Intel 8086

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  1. Intel 8086

  2. Registers • (16-bit) registers: • Data reg. – to hold data for an op. • Address reg – to hold addr of an instruction or data • Status reg / FLAGS reg

  3. 1. Data reg - 4 • AX • BX • CX • DX High byte – H Low byte – L AX  AH + AL

  4. AX – Accumulator reg • Preferred reg to use in arith/logic/data transfer instructions • Multiplication or Division ops.  one of the nos. must be in AX or AL • I/O operations also require the use of AX/AL

  5. BX – Base reg • It also serves as an Address reg.

  6. CX - Count reg • Loop counter • REP – repeat [in string operations] • CL  as a count in instructions that shift and rotate bits

  7. DX – data reg • Used in MUX and Division • Used in I/O ops.

  8. Registers • (16-bit) registers: • Data reg. – to hold data for an op. • Address reg – to hold addr of an instruction or data • Status reg / FLAGS reg

  9. 2. Address reg. a. Segment reg  CS, DS, SS, ES b. Pointer & index reg  Si, DI, SP, BP, IP

  10. a. Segment regs. – 4 • Each memory byte has an address • 8086 proc assigns a 20-bit physical address to its memory locations • It is possible to address  220 = 1,048,576 = 1 MB of memory • 1st byte’s address: 0000 00000000 00000000 • 2nd byte’s address: 0000 00000000 00000001 • 3rd0000 00000000 00000010 …

  11. In HEX • 00000 • 00001 • 00002 . . . • FFFFFh

  12. 16-bit processor! 20-bit address!! Q. Where lies the problem?? • 20-bit addresses are bigger to fit in a 16-bit reg or memory word.

  13. টুকরা টুকরা Memory Segment • Partioning memory into segments • A memory segment is a block of 216 or 64K consecutive memory bytes • Segment number – for each segment • Q: How many bits for a segment number?  16 bits! – as each block has byte of 216

  14. Segment: Offset address • Within a segment, a memory location is specified by giving an offset. Memory location  Segment no. + Offset Segment:Offset  Logical Address

  15. A4FB:4827h •  offset 4827, within segment A4FB Q: How to get 20-bit physical address? • Shift the segment address 4 bits to the left (eqv. to multiplying by 10h) • Add the offset So, the Physical Address for A4FB:4827h ???

  16. Logical Address: A4FB:4827h A 4 F B 0 + 4 8 2 7 A 9 8 2 2h  Physical Address 20-bit Physical Address  16-bit Segment [after shifting] + 16-bit Offset

  17. CS, DS, SS, ES Machine lang.  - instruction [code] - data - stack [data structure – used by the proc to implement procedure/function calls] These are loaded into different memory segments, • Code segment - CS • Data segment - DS • Stack segment - SS

  18. ES – extra segment reg • If a prog needs to access a second data segment, use the ES register! • At any time – only 4 mem locations addressed by the 4 segment reg [C/D/S/E] are accessible Q: How many memory segments can remain active at a time?  only 4 memory segments are active

  19. Registers • (16-bit) registers: • Data reg. – to hold data for an op. • Address reg – to hold addr of an instruction or data • Status reg / FLAGS reg

  20. 2. Address reg. a. Segment reg  CS, DS, SS, ES b. Pointer & index reg  SI, DI, SP, BP, IP

  21. b. Pointer & Index reg. • Stack pointer – SP – with SS [??] to access the stack segment • Base pointer – BP – mainly to access data on the stack. Also to access data in other segments. • Source index – SI – to point to memory locations in the data segment addressed by DS [??] • Destination index – DI  same as SI – but for instructions of string operations – to access memory locations – addressed by ES [??]

  22. Instruction pointer [IP] reg. Q: Which registers so far are for data access or to access instructions? • All above are for data access! • CS [Code segment – under Segment reg.] contains segment no. of the next instruction. • IP contains the offset

  23. IP is updated each time an instruction is executed – so that it will point to the next instruction. Q: Can IP reg be directly manipulated by an instruction?  Unlike other registers - NO!

  24. Registers • (16-bit) registers: • Data reg. – to hold data for an op. • Address reg – to hold addr of an instruction or data • Status reg / FLAGS reg

  25. 3. Status Reg./FLAGS reg. • To indicate the status of the mP. • 1 flag == 1 bit • Y/N • 9 active bits – out of ?? Bits? Q: Types of flags? Some names? • Status flags – Zero flag, Carry flag, sign flag, parity, auxiliary flag and overflow flag • Control flags – interrupt flag, trap flag, direction flag

  26. 8086 Internal Configuration

  27. Simplified block diagram over Intel 8088 (a variant of 8086); 1=main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal data bus; 9=ALU; 10/11/12=external address/data/control bus

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