1 / 17

Integrating Analog/Mixed-Signal IP Blocks in SoCs

Integrating Analog/Mixed-Signal IP Blocks in SoCs. Design Automation & Test in Europe– DATE 2005 Yves Gagnon, CTO. Laser Fine Tuning Analog Virtual Components. Introduction.

dena
Download Presentation

Integrating Analog/Mixed-Signal IP Blocks in SoCs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Integrating Analog/Mixed-Signal IP Blocks in SoCs Design Automation & Test in Europe– DATE 2005 Yves Gagnon, CTO Laser Fine TuningAnalog Virtual Components

  2. Introduction • “The demand for highly compact, greater functionality portable electronics has driven the integration of analog and mixed-signal devices onto the same chip” –The global market for power supply and power management integrated circuits, 4th edition, Venture Development Corporation, Dec 2003 • “Engineering goal is shifting from cost performance to cost-performance-per-watt” -The death of microprocessors. September 2004, Embedded Systems Programming: Nick Tredennick and Brion Shimamoto

  3. Dealing with SoC Complexity • Various experts required • In-house expertise limited • Outsourcing required • Need Silicon Proven IP blocks • Therefore, SoC Integrator more than Maker

  4. Dealing with SoC Complexity “The average number of hard macros in an SoC has increased from an average of under 20 in 2001 to an average of almost 100 last year, and is scheduled to reach almost 200 this year. An extrapolation of that trend shows that the average will likely reach almost 400 next year and 600 in 2006” EE Design, By Enno Wein & Jacques Benkoski August 20, 2004

  5. Challenges in Analog IP Integration • Integration of Analog IP into SoC is a very complex task • Complexity in: • Placement • Routing • Noise Coupling • Process Variations

  6. Placement • Keep analog IP which uses external components close to the pads • Apply time honored placement roles: Keep noisy IP away from quite IP • Avoid Mechanical Stress: mechanical constraints reach their maximum at the die’s corners

  7. Routing • Separate Power and GND lines for Analog & Digital • Avoid routing over sensitive Analog IP blocks. • Use double guard rings deep N-well • Use Large Metal lines to the output to lower parasitic effects

  8. Pass Transistor close to pad (load regulation) • Avoid adjacent parallel bonding pad for Vin and Vout Pass Transistor VIN VOUT • Double guard ring • Make sure that all NMOS are in deep Nwell Controller REF Example: LDO Integration • Use Bypass external capacitor • Avoid corners • Avoid routing over reference or controller • Avoid hot spot close to reference

  9. Power switches closed to pads (Efficiency) • Double guard ring around the switches • NMOS power switches in Deep Nwell Inductor GND PWR Switches VIN PWM Controller • PGND and VSS (ripple) • Sensitive analog circuitry far from power switches • Use PWM signal for synchronization with sensitive circuitry. REF OSC VSS Example: DC-DC Integration • No routing over power switches • Avoid routing over reference and oscillator

  10. Process Variations • Cause random drift of component physical characteristics such as Vth, Rsh, Csh, etc… • Cause random drift of circuits specifications such as output voltage, TC, frequency, gain, resolution, linearity etc… • Has to be compensated using post manufacturing tuning technologies

  11. Laser Fine Tuning (FasTrim) Basics • Combat Process Variations • Transparent To Manufacturing Process • Foundry Independent • Easily Scalable To Geometries • Reduced Manufacturing Cost • Minor modifications to existing trimming machines • Greater Accuracy

  12. Voltage Reference Example

  13. Laser Fine Tuning – Vref Example

  14. Aging

  15. OCP-IP Role & Analog IP • Analog IP interface is different from Digital • SoC getting more complex • OCP-IP role is pivotal in defining the interface: • Allow for greater understanding for integration between Analog & Digital IPs • Allow for ease of integration and pave the way for plug & play analog IP integration

  16. Summary • SoCs are getting more complex, analog IP integration is a key factor for high performing, full featured SoC • SoC Integrator must follow integration rules to ensure the preservation of analog IP block performance in SoC environment. • Advanced post manufacturing tuning techniques, such as LTRIM’s FasTrim, are required for the integration of high-performance analog or mixed-signal IP blocks • OCP-IP role is pivotal to ease the integration of digital and analog IP

  17. Thank You LTRIM TECHNOLOGIES, Inc. Integrating Analog/Mixed-Signal IP Blocks in SoC

More Related