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DLS Digital Controller

DLS Digital Controller. Tony Dobbing Head of Power Supplies Group. Content of talk. Features and overview Problem of resolution FPGA program structure Performance Development program Conclusions. J A Dobbing. DLS Digital Controller Features.

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DLS Digital Controller

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  1. DLS Digital Controller Tony Dobbing Head of Power Supplies Group

  2. Content of talk • Features and overview • Problem of resolution • FPGA program structure • Performance • Development program • Conclusions J A Dobbing

  3. DLS Digital Controller Features • Implemented on Xilink Spartan FPGA (low cost). • Backward compatible with original PSI digital controller. • Direct Ethernet connection to computer control network via • Colibri PXA270 processor board running EPICS, • 312 MHz clock, 64 MB RAM, 32 MB Flash. • Direct Ethernet port for Fast Orbit Feedback, with low latency • (150 ms less than original PSI controller). • Remote parameter loading. • FPGA program loaded from PXA270 – remote software changes. • USB port for local control via Labview application. • 64 MB Flash memory (non-volatile), 64 MB DDR SRAM. • 50MHz Clock Oscillator. J A Dobbing

  4. ADC/DAC Components • 4 off 18 bit ADC AD7691, for current measurement, with • oversampling 22 bit precision is achieved. • 4 Channel 16 bit ADC AD974, for DC link voltage and output • voltage monitoring. • 4 Channel DAC LTC2604, to monitor internal signals from • front panel. J A Dobbing

  5. DLS Digital Controller Block Diagram Reset Other Controller Cards Xilinx Spartan 3S 1600E FPGA (serial port) FLASH Memory 4 x DAC 16 bit Power Converter RAM 4x ADC 16 bit Analog Sig. Dual USB UART 4X ADC 18 bit Service PC Programming Analog Sig. Control Interlocks, Digital I/O Computer Network PWM signal PWM synchronisation Colibri Module PXA270 Ethernet Link Timing System Front Panel Optical Input DC DC Fast Orbit Feedback System 24 V Ethernet Link Backplane J A Dobbing

  6. DLS Controller - Module FPGA USB Port Ethernet Ports PXA270 Optical Trig DAC O/P 18 bit ADC Cover J A Dobbing

  7. LabView Interface – Summary and Scope J A Dobbing

  8. LabView Interface – Parameters and Waveforms J A Dobbing

  9. The Problem of Resolution with a Digital Controller Resolution = Clock Period/PWM Period For a power supply operating with a PWM of 100 kHz and a 50 MHz processor clock. Resolution = 20ns/10 ms = 0.2% (which is not enough by far) J A Dobbing

  10. Xilink Quadrant Phase Shift • Solutions:- • Increase clock frequency. • Xilink output quadrant phase shift, effectively increases • resolution to 4 times clock frequency. • E.g. 200 MHz clock with phase shifting gives 125 ppm • resolution for 100 kHz PWM. • Better but still not enough! J A Dobbing

  11. DLS Controller PWM Resolution 5 ns PWM resolution with 20 ns clock J A Dobbing

  12. Clock Pulse Averaging Convert to clock pulses Round to nearest integer + K + Modulation Index Integer number of clock pulses/quadrants to PWM generator + Sum - Sum errors and add running total to next cycle Average PWM output resolution is now limited only by computation word length. J A Dobbing

  13. Spartan 3E FPGA Structure • 3688 Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables that implement logic plus storage elements. • CLBs perform a wide variety of logical functions as well as store data. • 376 Input/Output Channels with Blocks (IOBs) controlling the flow of data between the I/O pins and the internal logic of • the device. Each IOB supports bidirectional data flow plus 3-state operation. • 648 Kbits Block RAM provides data storage in the form of 18-Kbit dual-port blocks. • 36 Dedicated Multiplier Blocks. • Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, • dividing, and phase-shifting clock signals. J A Dobbing

  14. FPGA Program Structure Protection Register ADC interface Scaling and filtering Feedback Modulation index to clock pulses PWM Generation Register Register Register Register Load 64 clock pulses or 1.28 ms J A Dobbing

  15. Controller Performance - ADC Noise The noise level of the output current, when Power Supply is running at 1 A J A Dobbing

  16. Controller Performance - Resolution 100mA/5Hz Waveform and Resulting Unfiltered Output Current and Measured Output Current Filtered at 100 Hz. Waveform Unfiltered Output Current Filtered Output Current J A Dobbing

  17. Controller Performance - Stability Stability over 20h with 100 mH Load J A Dobbing

  18. Controller Performance - Linearity J A Dobbing

  19. Development Programme for Booster Fast Orbit Feedback System • One controller presently operating on Booster corrector. • Upgrade 11 Booster corrector controllers in June 2012. • Upgrade remaining 33 Booster corrector controllers in August 2012. • Develop feedback algorithm to exploit reduced latency. • Upgrade Storage Ring FOFB system. J A Dobbing

  20. Conclusions • All diamond’s power supplies use the original very successful PSI • digital controller. • The Cirrus ADC used in this controller is no longer available. • Diamond now has its own replacement, that is pin compatible and • has significantly reduced latency, which makes it better for fast orbit • feedback applications. • The PXA270 processor eliminated the need for additional hardware • between the power supply and computer control network. J A Dobbing

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