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Memory

Memory. Latches: 1-bit memory circuits SR latch (S=Set, R=Reset) Set/Reset control signals Memory value and its complement as outputs D latch (D = Data) like SR, but avoids problem of S = R = 1 S comes from D; R comes from D’ Clocked latch: clock input as enable signal. An SR Latch.

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Memory

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  1. Memory • Latches: 1-bit memory circuits • SR latch (S=Set, R=Reset) • Set/Reset control signals • Memory value and its complement as outputs • D latch (D = Data) • like SR, but avoids problem of S = R = 1 • S comes from D; R comes from D’ • Clocked latch: clock input as enable signal

  2. An SR Latch

  3. A Clocked D Latch

  4. Flip-Flops • Flip-flops have same function as latches • Flip-flops are edge-triggered • Latches are level-triggered • Flip-flops typically used in industry

  5. D Flip-Flop

  6. Registers • Essentially a group of flip-flops • Common control signals • Different data signals • Distinct from main memory and cache • Typically found at the heart of the CPU

  7. 2-bit, 8-bit Memory Chips

  8. A 4 x 3 Memory Circuit

  9. Memory Circuit Notes • Data input lines (typically word size) • Data output lines (also word size) • Address lines • typically less than word size per memory IC • chip select line • Read/write indicator line • Output enable buffers (disconnects bus)

  10. A 4 Mbit Memory Chip

  11. 4 Mbit Memory Chip Notes • Multiple chips in a series • Chip select = highest order address bit(s) • 512 x 1024 possible addresses • Each address has 8 bits of data • Control signal for reading/writing (WE) • Control signal for output enable (OE) • Control signals are asserted to indicate “on”

  12. Cache (pp. 77-80, 293-298) • Spatial locality and temporal locality • Split into two areas: data and instructions • Mean access time = c + (1 - h) * m • Where c is cache access time • And h is the hit ratio • And m is main memory access time • Cache lines: fixed-size blocks and tags • Direct-mapped versus set-associative

  13. RAM Chips • SRAM: flip-flops • S = static (i.e. “power’s always on”) • DRAM: capacitors • less circuitry/space/power, but slower • D = dynamic (i.e. “refreshed periodically”) • EDO: two-stage pipeline • FPM: fast page mode (cache nearby words) • SDRAM: S=synchronous with clock • DDR: double data rate (access on rise, fall)

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