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MC68HC11 Instruction Set Overview

Understand logic, arithmetic, data handling, and control instructions for the MC68HC11 microcontroller. Learn move, alter data, logic, arithmetic, data test, control, and miscellaneous instructions.

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MC68HC11 Instruction Set Overview

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  1. ECE 447: Lecture 12 Logic, Arithmetic, Data Test and Control Instructions of MC68HC11

  2. ECE 447: Groups of Instructions (1) 1. Data handling instructions a. Move instructions (e.g., load, store, exchange) b. Alter data instructions (e.g., clear, increment, decrement) c. Edit instructions (e.g., shift, rotate) 2. Logic instructions (e.g., and, or, xor) 3. Arithmetic instructions (e.g., add, subtract, multiply, divide, negate)

  3. ECE 447: Groups of Instructions (2) 4. Data test instructions (e.g. compare, test, bit test) 5. Control instructions (e.g., jump, branch) 6. Condition code instructions (e.g., set carry, clear overflow flag) 7. Stack operations (e.g. push, pull)

  4. ECE 447: Groups of Instructions (3) 8. Subroutine-related instructions (e.g. jump to subroutine, return from subroutine) 9. Interrupt-related instructions (e.g. software interrupt, return from interrupt, wait for interrupt) 10. Miscellaneous instructions (e.g. no operation, stop)

  5. ECE 447: Move Instructions (1) N Z V C 1. memory  register LDA[A, B] M LD[D, X, Y, S] M 2. register  memory STA[A, B] M ST[D, X, Y, S] M 3. register  register TAB, TBA 4. memory  memory 0 – IMM, DIR, EXT, IND 0 – DIR, EXT, IND 0 – INH

  6. ECE 447: Move Instructions (2) N Z V C 1. register  register XGD[X, Y] – – – – INH

  7. ECE 447: Alter Data Instructions (1) N Z V C 1. 0  register CLR[A, B] 2. 0  memory CLR M 0 1 0 0 INH 0 1 0 0 EXT, IND

  8. ECE 447: Alter Data Instructions (2) N Z V C 3. increment X++ INC[A, B] INC M IN[X, Y] 4. decrement X-- DEC[A, B] DEC M DE[X, Y] INH EXT, IND INH – – – – INH EXT, IND INH – – – –

  9. ECE 447: Logic Instructions (1) N Z V C 1. AND Acc & M  Acc AND[A, B] M 2. OR Acc | M  Acc ORA[A, B] M 3. XOR Acc  M  Acc EOR[A, B] M 0 – IMM, DIR, EXT, IND 0 – IMM, DIR, EXT, IND 0 – IMM, DIR, EXT, IND

  10. ECE 447: Logic Instructions (2) N Z V C 3. complement X  X COM[A, B] COM M 4. bit set M | mask  M BSET M, mask 5. bit clear M & mask  M BCLR M, mask INH EXT, IND 0 1 DIR, IND 0 – DIR, IND 0 –

  11. ECE 447: Arithmetic Instructions (1) N Z V C 1. addition Acc + M [+ C]  Acc ADD[A, B, D] M ADC[A, B] M 2. subtraction Acc – M [-C]  Acc SUB[A, B, D] M SBC[A, B] M IMM, DIR, EXT, IND IMM, DIR, EXT, IND

  12. ECE 447: Arithmetic Instructions (2) 3. negation -X NEG[A, B] NEG M INH EXT, IND 4. addition Reg + B  Reg ABA AB [X, Y] 5. subtraction A – B  A SBA INH – – – – INH

  13. ECE 447: Signed vs. Unsigned B = b7 b6 b5 b4 b3 b2 b1 b0 Unsigned number weights 128 64 32 16 8 4 2 1 B = b7 b6 b5 b4 b3 b2 b1 b0 7  B = b020 + b121 + b222 + b323 + b424 + b525 + b626 + b727 = bi2i i=0 Signed number weights -128 64 32 16 8 4 2 1 B = b7 b6 b5 b4 b3 b2 b1 b0 6  bi2i B = b020 + b121 + b222 + b323 + b424 + b525 + b626 - b727 = - b727 + i=0

  14. ECE 447: 2’s Complement Representation X>0 0 X<0 k=4 X 0 X+2k = X+1 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 34 5 6 7 0 1 2 34 5 6 7 8 9 10 11 12 13 14 15

  15. ECE 447: Unsigned vs. Signed Addition Programmer Machine Unsigned mind Signed mind weight 128 64 32 16 8 4 2 1 carry 1 1 1 X Y S 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 + = x3 y3 x2 y2 x6 y6 x5 y5 x1 y1 x7 y7 x4 y4 x0 y0 FA FA FA FA FA FA FA FA c4 c3 c7 c6 c2 c8 c5 c1 s3 s2 s6 s5 s1 s7 s4 s0

  16. ECE447: Definitions of CCR flags (1) Zero flag - Z zero result Z = 1 if result = 0 0 otherwise Negative flag- N negative result N = sign bit of the result r7 - for 8-bit operands r15 - for 16-bit operands

  17. ECE447: Definitions of CCR flags (2) Carry flag - C out-of-range for unsigned numbers C = 1 if result > MAX_UNSIGNED or result < 0 (a borrow occurred) 0 otherwise where MAX_UNSIGNED = 28-1 for 8-bit operands (registers A, B) 216-1 for 16-bit operands (register D) Overflow flag - V out-of-range for signed numbers V = 1 if result > MAX_SIGNED or result < MIN_SIGNED 0 otherwise where MAX_SIGNED = 27-1 for 8-bit operands (registers A, B) 215-1 for 16-bit operands (register D) MIN_SIGNED = -27 for 8-bit operands (registers A, B) -215 for 16-bit operands (register D)

  18. ECE 447: Overflow of Signed Numbers Indication of overflow Negative + Negative = Positive Positive + Positive = Negative Formulas Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1

  19. ECE 447: Arithmetic Instructions (3) N Z V C 1. unsigned multiplication A x B  D MUL 2. unsigned division D/IX  IX D mod IX  D IDIV 3. unsigned fractional division D < IX (scaled by 216) D/ IX  IX (scaled by 216) D mod IX  D 4. decimal adjustment DAA – – – INH – 0 INH – FDIV INH ? INH

  20. ECE 447: Sign Extension Extending the number of bits of a signed number xk-1xk-2 … x1x0 X yk’-1yk’-2 … ykyk-1yk-2 … y1y0 Y two’s complement xk-1 xk-1 xk-1 . . .xk-1xk-2 … x1x0

  21. ECE 447: Data Test Instructions N Z V C 1. comparison R - M CMP[A, B] M CP[D, X, Y] M IMM, DIR, EXT, IND 2. comparison A – B CBA INH 3. test register TST[A, B] 0 0 INH

  22. ECE 447: Data Test Instructions N Z V C 4. test memory TST M 5. Bit test Acc & M BIT[A, B] M 0 0 EXT, IND IMM, DIR, EXT, IND 0 –

  23. ECE 447: Branch Instructions (1) N Z V C – – – – REL after comparison register vs. memory unsigned numbers signed numbers BHI higher > BLO lower < BHS higher or same  BLS lower or same  BGT greater than > BLT less than < BGE greater than or equal  BLE less than or equal  BEQ equal = BNE not equal 

  24. ECE 447: Brach Instructions (2) after arithmetic operations (testing for overflow) unsigned numbers signed numbers BCS carry set BCC carry clear BVS overflow set BVC overflow clear after testing register or memory BPL plus  0 BMI minus < 0 unconditional BRA always BRN never

  25. ECE 447: Bit test and branch instructions 1. Bit test and branch branch if (M & mask) == 0 – – – – BRCLR M, mask label DIR, IND 2. Bit test and branch branch if (M & mask) == 0 – – – – BRSET M, mask label DIR, IND

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