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EECE 476: Computer Architecture Slide Set #1: Introduction. Instructor: Tor Aamodt. Computer Architecture: What?. Problem. Algorithm Program ( + OS + Network ) ISA (Instruction Set Arch) Microarchitecture Circuits. Electronic Devices. Computer Architecture: Where?.
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EECE 476: Computer ArchitectureSlide Set #1: Introduction Instructor: Tor Aamodt
Computer Architecture: What? Problem Algorithm Program ( + OS + Network ) ISA (Instruction Set Arch) Microarchitecture Circuits Electronic Devices
Computer Architecture: Why? "What a Computer is to me: is the most remarkable tool that we have ever come up with, and it is like the equivalent of a bicycle to our minds” -- Steve Jobs
Advancing Computer Systems without Technology Progress DARPA/ISAT Workshop, March 26-27, 2012 Mark Hill & Christos Kozyrakis 1981: IBM 5150 2007: iPhone 2012: Datacenter 1971: Intel 4004
Computer Architecture: How? Architecture Design (result ~ block diagram) hardware design Market Opportunities & Requirements Achievable Product implementation constraints (area, frequency, power) How to evaluate architecture designs? Cycle-level timing simulator usually developed “in house”. Public (academic research) simulators: SimpleScalar, Marss86, gem5, GPGPU-Sim
Computer Architecture: When? Architecture Design: - Cycle level simulator Hardware Design: - VHDL/Verilog - circuit design - layout Image: Justin Rattner
Qualcomm (multi-site team), March 2012 Position: “SoC Architect” • Architect market-leading mobile SoC products • …. provide quantitative justification for architectural directions; • Directly apply computer architecture knowledge of CPUs, GPUs, DSPs, cache coherency, virtual memory, etc.; Skills • Hands-on experience in using and modifying simulators and performance/power models… • Proficiency in C/C++/SystemC programming. • 0-3 years post-educational work experience Education Bachelor’s or Master’s, Computer Science, Electrical, and/or Computer Engineering; Ph.D. is a plus
EECE 476 Topics • Fundamentals of Computer Design • Instruction Set Architecture Design • Pipelining • Out of order execution • Branch prediction • Superscalar instruction issue • Speculative execution • Caches • Virtual Memory • Cache Coherence
EECE 476 Marks • Participation (clickers / flipped classroom quizzes) 5% • Assignments(alone or in pairs) 20% • Quizzes (best 2 of 3; study group bonus) 10% • Midterm: Mon. Oct. 28 in lecture 20% • Exam: 45%
Complexity vs. Ambiguity • WARNING: Questions may contain ambiguities • Why? • Computers are complex systems • We tend to abstract lower level design details to focus on higher level design • On the job you might ask for clarifications. • On quiz/midterm/exam: please state your assumptions.
Textbook? OPTIONAL: Computer Architecture: A Quantitative Approach, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 5th Edition.
Clickers (Required) • 5% of final grade. Count number of questions answered (participation, not correctness). • Answer 90% of questions to get full 5%. • Start counting next week. • Register your clicker online.
Flipped Class? • Zero or more lectures may be delivered by video and we will work through examples in the regular lecture time in a participatory manner. • Will give you at least 48 hours notice (probably more).
Course Website? http://www.ece.ubc.ca/~aamodt/teach/476-2013/ Check here frequently for important news.