An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

1. An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge Adviser: Chao-Lieh Chen Student: Shih-Hao Lin 0052802 Yi-Ming Huang 0052811 Keng-Chih Liu 0052810

2. Outline • Introduction • Proposed TAM for AMBA-based SOC • Proposed Test-Access Architecture • On/Off-Chip Bus Bridge With Test Controllability • Operation of the TR-Bridge • Project • Schedule • Division of work

3. Introduction

4. Proposed TAM for AMBA-based SOC • The main contribution of our technique is to reuse the on/off chip bus bridge as a test interface during the test mode. • The AHB master component on the bridge is reused as an interface between the ATE and the chip under test, and then, the ATE acts as a virtual bus master. • By utilizing the functional buses as dedicated test paths and eliminating the bus-direction turnaround delays. • In this paper, the bridge with the test controllability is referred to as a test-ready bridge.

5. Proposed Test-Access Architecture

6. On/Off-Chip Bus Bridge With Test Controllability

7. On/Off-Chip Bus Bridge With Test Controllability

8. Operation of the TR-Bridge

9. Project • Midterm project AHB bus • Final project Hybrid Test Interface Controller

10. Schedule

11. Division of work • Shih-Hao Lin 撰寫程式實現HTIC區塊 • Yi-Ming Huang 撰寫程式實現AHB Master區塊 • Keng-Chih Liu 搜尋實現過程中之相關資訊

12. Q: • TIC and HTIC difference • Functional test V.S. Structural test • Test Stimuli

13. TIC and HTIC difference(1/2) AMBA™ Specification (Rev 2.0)

14. TIC and HTIC difference(2/2)

15. Functional test V.S. Structural test

16. Test Stimuli