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Arithmetic Circuits (Part II) Randy H. Katz University of California, Berkeley Fall 2005

Learn about BCD addition, multiplier circuit design, and sequential multiplier overview. Explore techniques like partial product accumulation and decomposition. Get insights on building parallel carry-outs. Discover how to implement an 8x8 multiplier using 4x4 multipliers efficiently.

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Arithmetic Circuits (Part II) Randy H. Katz University of California, Berkeley Fall 2005

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  1. Arithmetic Circuits(Part II)Randy H. KatzUniversity of California, BerkeleyFall 2005

  2. BCD Circuits Combinational Multiplier Circuit Design Case Study: 8 Bit Multiplier Sequential Multiplier Circuit Overview

  3. BCD Addition BCD Number Representation Decimal digits 0 thru 9 represented as 0000 thru 1001 in binary Addition: 5 = 0101 3 = 0011 1000 = 8 5 = 0101 8 = 1000 1101 = 13! Problem when digit sum exceeds 9 Solution: add 6 (0110) if sum exceeds 9! 5 = 0101 8 = 1000 1101 6 = 0110 1 0011 = 1 3 in BCD 9 = 1001 7 = 0111 1 0000 = 16 in binary 6 = 0110 1 0110 = 1 6 in BCD

  4. BCD Addition Adder Design A B A B A B A B 3 3 2 2 1 1 0 0 CO F A CI CO F A CI CO F A CI CO F A CI Cin S S S S A1 1 1XX A2 1X1X CO F A CI CO F A CI 0 S S Cout S S S S 3 2 1 0 Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

  5. Combinational Multiplier Basic Concept multiplicand multiplier 1101 (13) 1011 (11) 1101 product of 2 4-bit numbers is an 8-bit number * 1101 Partial products 0000 1101 10001111 (143)

  6. Combinational Multiplier Partial Product Accumulation A1 B1 A1 B0 A0 B1 A0 B0 A0 B0 A3 B3 A3 B0 A2 B1 A1 B2 A0 B3 A2 B2 A2 B0 A1 B1 A0 B2 A3 B1 A2 B2 A1 B3 A3 B3 A3 B2 A2 B3 S7 S6 S4 S5 S3 S2 S1 S0

  7. Combinational Multiplier Partial Product Accumulation A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B 3 3 3 2 2 3 3 1 2 2 1 3 3 0 2 1 1 2 0 3 2 0 1 1 0 2 0 1 1 0 0 0 F A HA HA HA F A F A F A F A F A HA F A F A S S S S S S S S 7 6 5 4 3 2 1 0 Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates!

  8. Combinational Multiplier Another Representation of the Circuit Sum In Building block: full adder + and X Y F A A B Cin Cout CO CI S Sum Out A3 A2 A0 A1 B0 A3 B0 A2 B0 A1 B0 A0 B0 0 C C C C S S S S B1 A3 B1 A2 B1 A1 B1 A0 B1 0 C C C C S S S S B2 A3 B2 A2 B2 A1 B2 A0 B2 0 C C C C S S S S B3 A3 B3 A2 B3 A1 B3 A0 B3 0 C S S S S P7 P6 P5 P4 P3 P2 P1 P0 4 x 4 array of building blocks

  9. Case Study: 8 x 8 Multiplier Problem Decomposition How to implement 8 x 8 multiply in terms of 4 x 4 multiplies? A7-4 B7-4 A3-0 B3-0 * A3-0 * B3-0 = PP0 8 bit products A7-4 * B3-0 = PP1 A3-0 * B7-4 = PP2 A7-4 * B7-4 = PP3 P15-12 P11-8 P7-4 P3-0 P3-0 = PP0 P7-4 = PP0 + PP1 + PP2 P11-8 = PP1 + PP2 + PP3 P15-12 = PP3 3-0 + Carry-in 3-0 3-0 3-0 + Carry-in 7-4 7-4 3-0 + Carry-in 7-4

  10. Case Study: 8 x 8 Multiplier Calculation of Partial Products Use 4 4x4 multipliers to create the 4 partial products

  11. Case Study: 8 x 8 Multiplier Three-At-A-Time Adder Clever use of the Carry Inputs Sum A[3-0], B[3-0], C[3-0]: Two Level Full Adder Circuit Note: Carry lookahead schemes also possible!

  12. Case Study: 8 x 8 Multiplier Three-At-A-Time Adder with TTL Components Full Adders (2 per package) Full Adder Full Adder Full Adder Full Adder Standard ALU configured as 4-bit cascaded adder (with internal carry lookahead) 4-bit ALU/Adder Note the off-set in the outputs

  13. Case Study: 8 x 8 Multiplier Accumulation of Partial Products FA FA FA FA FA FA FA FA 4-bit ALU/Adder 4-bit ALU/Adder 4-bit ALU/Adder Just a case of cascaded three-at-a-time adders!

  14. Case Study: 8 x 8 Multiplier The Complete System (Actual TTL packages)

  15. Case Study: 8 x 8 Multiplier Package Count and Performance 4 74284/74285 pairs = 8 packages 4 74183, 3 74181, 1 74182 = 8 packages 16 packages total Partial product calculation (74284/285) = 40 ns typ, 60 ns max Intermediate sums (74183) = 9 ns/20ns = 15 ns average, 33 ns max Second stage sums w/carry lookahead 74LS181: carry G and P = 20 ns typ, 30 ns max 74182: second level carries = 13 ns typ, 22 ns max 74LS181: formations of sums = 15 ns typ, 26 ns max 103 ns typ, 171 ns max

  16. 4-Bit Multiplier Example: 3 x 4 = 12 Four cycles to completion Cycle Multiplier Multiplicand Product Initialize 0011 0000 0100 0000 0000 Cycle 0, Multiplier[0]=1 0001 0000 1000 0000 0100 Cycle 1, Multiplier[0]=1 0000 0001 0000 0000 1100 Cycle 2, Multiplier[0]=0 0000 0010 0000 0000 1100 Cycle 3, Multiplier[0]=0 0000 0100 0000 0000 1100 Sequential Multiplier Product = 0 For i = 0 to 3 do If Multiplier[0] = 1 then Product = Product + Multiplicand Shift right the Multiplier Shift left the Multiplicand

  17. Datapath and Control Block Diagram External load signals for Multiplier and Multiplicand Low order bit of multiplier: if 0, shift; if 1, shift and add Sequential Multiplier 8 Load1 ‘0’ Multiplier Digit Clock Start Digit 8 8 Load2 Multiplicand ‘0’ Shift Control 16 16 Accumulator Shift Clear Load3 16 Clear Product Load3 16

  18. State Diagram One state for each bit Sequential Multiplier Reset Start’ Idle Start/Clear S0 Digit/Load3,ShiftDigit’/Shift S1 Digit/Load3,ShiftDigit’/Shift S2 Digit/Load3,ShiftDigit’/Shift S3 Digit/Load3,ShiftDigit’/Shift S4 Digit/Load3,ShiftDigit’/Shift S5 Digit/Load3,ShiftDigit’/Shift S6 Digit/Load3,ShiftDigit’/Shift S7 Digit/Load3,ShiftDigit’/Shift

  19. Control Timing Behavior Sequential Multiplier Clk State Start Clear Load Shift Idle S0 S1 S2 S3 S4 S5 S6 S7 Idle Digit0 Digit1 Digit2 Digit3 Digit4 Digit5 Digit6 Digit7

  20. Slightly Revised Block Diagram If multiplier low order bit is 0 than assert 0 into accumulator Else pass multiplicand through to accumulator Simplifies the control! Sequential Multiplier 8 Load1 ‘0’ Multiplier Digit 8 8 Load2 Clock Start Multiplicand ‘0’ Load3-Shift 16 Control Pass or Zero Pass/Zero’ 16 16 Accumulator Clear Load3-Shift 16 Clear Product 16

  21. Revised State Diagram Fewer control outputs! Sequential Multiplier Reset Start’ Idle Start/Clear S0 Load3-Shift S1 Load3-Shift S2 Load3-Shift S3 Load3-Shift S4 Load3-Shift S5 Load3-Shift S6 Load3-Shift S7 Load3-Shift

  22. Symbolic/Encoded State Transition Table State assignment chosen as follows: Idle state set to 0000, i.e., START resets the state FFs States S0 to S7 set to 1000 to 1111, easy to implement as a counter Sequential Multiplier Current State Start Next State Clear Load3-Shift Idle 0000 0 0000 Idle 0 0 Idle 0000 1 1000 S0 1 0 S0 1000 - 1001 S1 0 1 S1 1001 - 1010 S2 0 1 S2 1010 - 1011 S3 0 1 S3 1011 - 1100 S4 0 1 S4 1100 - 1101 S5 0 1 S5 1101 - 1110 S6 0 1 S6 1110 - 1111 S7 0 1 S7 1111 - 0000 Idle 0 1

  23. Tricky encoding scheme to reduce the number of stages in a binary multiplier Considers two bits at a time rather than one—this cuts the number of multiplier steps in half Each step is slightly more complex compared to the simple multiplier, but is almost as fast as the basic multiplier stage that it replaces Booth Multiplier Searching for ways to speed up the basic multiply step

  24. 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Rather than shift multiplier right and multiplicand left, we can shift BOTH the product and the multiplier to the right … Alternative Multiply Hardware Multiplicand 32 bits 32-bit ALU Shift Right Product (Multiplier) Control Write 64 bits

  25. Multiplicand Product0010 0000 0011 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Multiply Control Start Product0 = 1 1. Test Product0 = 0 Product0 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  26. Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0010 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 If ALU can subtract as well as add, get same result as follows: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 For example 0010 x 0110 0000 shift (0 in multiplier)– 0010 sub(first 1 in multiplier)0000 shift (mid string of 1s) + 0010 add (prior step had last 1) 00001100 Motivation for Booth’s Algorithm Just add 1111110 (twos complement of 2)

  27. Recode each 1 in multiplier as “+2-1” Converts sequences of 1 to 10…0(-1) Might reduce the number of 1’s Booth Multiplier: an Introduction 0 0 1 1 11 1 1 0 0 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 0 1 0 0 0 0 0 -1 0 0

  28. If you use the last row in multiplication, you should get exactly the same result as using the first row (after all, they represent the same number!) Recoding (Encoding) Example 0 1 1 0 111 0 0 0 1 0 (+1 -1) (+1 -1) (+1 -1) (+1 -1)(+1 -1) (+1 -1) +1 0 -1 +1 0 0 -1 0 0 +1 -1 0

  29. Sign extension Booth Multiplication Example 0 0 1 1 0 6x 0 1 1 1 0 14 +1 0 0 -1 0 0 0 0 0 0 1 1 0 1 0 (-6) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 84 1 1 1

  30. Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift is faster than add, it is advantageous to replace adds and subs with shifts) Basic idea: replace a string of 1s in multiplier with an initial subtract for rightmost 1 in a run of 1’s, then later add back a 1 for the bit to the left of the last 1 in the run Booth’s Algorithm: Implementation Approach end of run beginning of run middle of run 0 1 1 1 1 0 –1 + 10000 01111

  31. 1a. P = P - m 1110 + 1110 1110 01110 shift P (sign ext) 1b. 0010 1111 00111 11 -> nop, shift 2. 0010 1111 10011 11 -> nop, shift 3. 0010 1111 11001 01 -> add 4a. 0010 + 0010 0001 11001 shift 4b. 0010 0000 1110 0 done Booth’s Example (2 x 7) Operation Multiplicand Product next? 0. initial value 0010 0000 01110 10 -> sub

  32. 1a. P = P - m 1110 +1110 1110 11010shift P (sign ext) 1b. 0010 1111 01101 01 -> add + 0010 2a. 0001 01101shift P 2b. 0010 0000 10110 10 -> sub + 1110 3a. 0010 1110 10110 shift 3b. 0010 1111 0101 111 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 10101 done Booth’s Example (2 x -3) Operation Multiplicand Product next? 0. initial value 0010 0000 11010 10 -> sub

  33. Lecture Review We have covered: • BCD Adders • Simple extension of binary adders • • Multipliers • 4 x 4 multiplier: partial product accumulation • extension to 8 x 8 case • Sequential Multipliers • Booth Multiply Step • Recoding to speed up the calculation

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