Roadmap and Vision for Physical Design: Challenges and Solutions

1. A Roadmap and Vision for Physical DesignISPD-2002April 9, 2002Andrew B. Kahng, UCSD CSE & ECE Departmentsemail: abk@ucsd.eduURL: http://vlsicad.ucsd.edu

2. Outline • What we need • ITRS challenges, logical/circuit/physical needs • SRC needs • What we do • Allocation of effort, versus needs and resources • Harmful practices • What we need to do • Coopetition • Shared red bricks • What we need to do, II • A top-10 list

3. The “Red Brick Wall” - 2001 vs. 1999 Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876

4. Roadmap Acceleration and Deceleration 2001 versus 1999 Year of Production: 1999 2002 2005 2008 2011 2014 DRAM Half-Pitch [nm]:180 130100 70 50 35 Overlay Accuracy [nm]: 65 45 3525 20 15 MPU Gate Length [nm]: 14085-90 65 45 30-32 20-22 CD Control [nm]:1496 4 3 2 TOX (equivalent) [nm]: 1.9-2.51.5-1.91.0-1.5 0.8-1.2 0.6-0.8 0.5-0.6 Junction Depth [nm]: 42-70 25-4320-3316-26 11-19 8-13 Metal Cladding [nm]: 17 13 10 000 Inter-Metal Dielectric K: 3.5-4.0 2.7-3.5 1.6-2.2 1.5 Source: A. Allan, Intel

5. An ITRS Analogy • ITRS is like a car • Before, two drivers (husband = MPU, wife = DRAM) • The drivers looked mostly in the rear-view mirror (destination = “Moore’s Law”) • Many passengers in the car (ASIC, SOC, Analog, Mobile, Low-Power, Networking/Wireless, …) wanted to go different places • This year: • Some passengers became drivers • All drivers explain more clearly where they are going • See the new “System Drivers” Chapter of the ITRS

6. Parameter Type 99 01 03 05 07 10 13 16 Vdd MPU 1.5 1.2 1.0 0.9 0.7 0.6 0.5 0.4 LOP 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 LSTP 1.3 1.2 1.2 1.2 1.1 1.0 0.9 0.9 Vth (V) MPU 0.21 0.19 0.13 0.09 0.05 0.021 0.003 0.003 LOP 0.34 0.34 0.36 0.33 0.29 0.29 0.25 0.22 LSTP 0.51 0.51 0.53 0.54 0.52 0.49 0.45 0.45 Ion (uA/um) MPU 1041 926 967 924 1091 1250 1492 1507 LOP 636 600 600 600 700 700 800 900 LSTP 300 300 400 400 500 500 600 800 CV/I (ps) MPU 2.00 1.63 1.16 0.86 0.66 0.39 0.23 0.16 LOP 3.50 2.55 2.02 1.58 1.14 0.85 0.56 0.35 LSTP 4.21 4.61 2.96 2.51 1.81 1.43 0.91 0.57 Ioff (uA/um) MPU 0.00 0.01 0.07 0.30 1.00 3 7 10 LOP 1e-4 1e-4 1e-4 3e-4 7e-4 1e-3 3e-3 1e-2 LSTP 1e-6 1e-6 1e-6 1e-6 1e-6 3e-6 7e-6 1e-5 HP / LOP / LSTP Device Roadmaps

7. Silicon Complexity Challenges • Impact of process scaling, new materials, new device/interconnect architectures • Non-ideal scaling (leakage, power management, circuit/device innovation, current delivery) • Coupled high-frequency devices and interconnects (signal integrity analysis and management) • Manufacturing variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools) • Scaling of global interconnect performance (communication, synchronization) • Decreased reliability (SEU, gate insulator tunneling and breakdown, joule heating and electromigration) • Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost)

8. System Complexity Challenges • Exponentially increasing transistor counts, with increased diversity (mixed-signal SOC, …) • Reuse (hierarchical design support, heterogeneous SOC integration, reuse of verification/test/IP) • Verification and test (specification capture, design for verifiability, verification reuse, system-level and software verification, AMS self-test, noise-delay fault tests, test reuse) • Cost-driven design optimization (manufacturing cost modeling and analysis, quality metrics, die-package co-optimization, …) • Embedded software design (platform-based system design methodologies, software verification/analysis, codesign w/HW) • Reliable implementation platforms (predictable chip implementation onto multiple fabrics, higher-level handoff) • Design process management (team size / geog distribution, data mgmt, collaborative design, process improvement)

9. Big-Picture Design Technology Crises Incremental Cost Per Transistor Test Manufacturing Manufacturing • 2-3X more verification engineers than designers on microprocessor teams • Software = 80% of system development cost (and Analog design hasn’t scaled) • Design NRE > 10’s of $M  manufacturing NRE $1M • Design TAT = months or years  manufacturing TAT = weeks • Without DFT, test cost per transistor grows exponentially relative to mfg cost Where is the Physical Design? SW Design NRE Cost Turnaround Time Verification HW Design

10. SRC Grand Challenges 1. Extend CMOS to its ultimate limit 2. Support continuation of Moore's Law by providing a knowledge base for CMOS replacement devices 3. Enable Wireless/Telecomm systems by addressing technical barriers in design, test, process, device and packaging technologies 4. Create mixed-domain transistor and device interconnection technologies, architectures, and tools for future microsystems that mitigate the limitations projected by ITRS 5. Search for radical, cost effective post NGL patterning options 6. Provide low-cost environmentally benign IC processes 7. Increase factory capital utilization efficiency through operational modeling 8. Provide design tools and techniques which enhance design productivity and reduce cost for correct, manufacturable and testable SOC's and SOP's 9. Enable low power and low voltage solutions for mobile/battery conserving applications through system and circuit design, test and packaging approaches. 10. Enable very low cost components 11. Provide tools enabling rapid implementation of new system architectures Where is the Physical Design?

11. Systems S3.2: Early Design Space Exploration S1.2: Low Power, Real-Time Algorithms and Architectures S4.1: On-Chip Communication S1.3: High Bandwidth and/or Low Power Communication S2.4: Deep Submicron Aware Microarchitectures, Accounting for Noise, Power, Timing, Interconnects, etc. S1.1: High Level Specifications of Complex Systems Circuits C1.2: Digital Low Power and/or Low Voltage Circuit Design C2.1: Mixed Signal Circuits on Advanced Technologies C2.4: Mixed Signal Low Power and/or Low Voltage Circuit Design C1.1: Digital Circuits on Advanced Technologies C2.3: Mixed Signal Design for Test C2.2: Mixed Signal Noise Immune and/or Tolerant Circuits SRC ICSS Key Technologies (Top 12) Where is the Physical Design?

12. ITRS Logical/Physical/Circuit Challenges • Efficient and predictable implementation • Scalable, incremental analyses and optimizations • Unified implementation/interconnect planning and estimation/prediction • Synchronization and global signaling • Heterogeneous system composition • Links to verification and test • Reliable, predictable fabric- and application-specific silicon implementation platforms • Cost-driven implementation flows • Variability and design-manufacturing interface • Uncertainty of fundamental chip parameters (timing, skew, matching) due to manufacturing and dynamic variability sources • Process modeling and characterization • Cost-effective circuit, layout and reticle enhancement to manage manufacturing variability • Increasing atomic-scale variability effects

13. ITRS Logical/Physical/Circuit Challenges • Silicon complexity, non-ideal device scaling and power management • Leakage and power management • Reliability and fault tolerance • Analysis complexity and consistent analyses / synthesis objectives • Recapture of reliability lost in manufacturing test • Circuit design to fully exploit device technology innovation • Support for new circuit families that address power and performance challenges • Implementation tools for SOI • Analog synthesis • Increasing atomic-scale effects • Adaptive and self-repairing circuits • Low-power sensing and sensor interface circuits; micro-optical devices

14. Placement and Routing Synthesis/Layout Integration Power Distribution and Analysis High Level Planning and Estimation Clocking Design and Analysis Above 15GHz Interconnect Synthesis and Analysis Timing Analysis and Verification Correct by Construction SRC CADT PD Research Needs (2002 Draft) Where are the ITRS challenges?

15. Outline • What we need • ITRS challenges, logical/circuit/physical needs • SRC needs • What we do • Allocation of effort, versus needs and resources • Harmful practices • What we need to do • Coopetition • Shared red bricks • What we need to do, II • A top-10 list

16. Our Resources • 6000 EDA R&D, worldwide (Gartner/Dataquest) • EDA tools revenue per designer has increased by 3.9% per year over past decade • Ratio of design value over design effort is perceived to decrease as level of abstraction moves downward from behavior to layout • PD is at most one-sixth (by market size, or by headcount) of EDA and design technology • 150-200 ISPD attendees, ~60 DAC/ICCAD/ISPD papers in PD domain, per year

17. Industry Semiconductor Industry: U.S. & Foreign Equipment, Materials & EDA Suppliers Government • Foreign Gov’ts • MEDEA+ • 6th Framework • LETI • IMEC • ASUKA • MIRAI • SELETE • STARC • U.S. Gov’t • NSF • DARPA • DoD S&T • DoE Research Funding Gap Study • C. Nuese, SRC • Research needs • Time frame 2008+ (50-, 35-, and 22-nm nodes in ITRS) • Assessed by SRC Science Area Directors (131 total tasks) • Research funding • 2001 used for all data • U.S., Europe, Japan and Asia-Pacific • Assumed % of R&D (or % of Sales) Source: C. Nuese / SRC

18. as % of as % of Industry funding for ITRS nodes Sales R&D By Semiconductor Industry 0.24% 2.0% By Semi Equipment Suppliers 0.06% 0.5% By Semi Material Suppliers 0.00% 0.2% By EDA suppliers 0.11% 0.5% Redundancy in WW Research Funding % Redund (Due to uncoordinated project funding 30% between different regions of the world) Lack of WW Research "Accessibility" % Accessible of Asian results to U.S. researchers 40% of European results to U.S. researchers 70% of U.S. results to Asian researchers 70% of European results to Asian researchers 70% of U.S. results to European researchers 80% of Asian results to European researchers 50% Forecast Change in Semiconductor Sales between -16.7% year 2000 & 2001 (in %) Funding Model Source: C. Nuese / SRC

19. Research Needs Summary U.S. Gov’t Funding Foreign Government Funding Foreign Government Funding 2001 Industry Funding Europe Japan & Asia-Pacific Europe Japan & Asia-Pacific $1,406M U.S. Gov’t Funding 2001 Industry Funding Research Needs Program Amount ($M) Program Amount ($M) European Community 6th Framework 95 Sub-0.1 micron Project 30 STARC (next phase) 21 MEDEA-Plus 23 SELETE (next phase) 31 $442M IMEC, LETI, Fraunhofer 55 MARAI 14 Other 25 $442M 198 96 Total Total $442M 131 (~ 0.8% of sales) 1,406 1,406 131 (~ 0.8% of sales) $548M U.S. $ 224M Europe $ 47M Japan $ 171M $990M $254M $254M $416M Research Funding Gap Results Foreign redundancy and inaccessibility significantly increase size of effective research gap. Source: C. Nuese / SRC

20. Anatomy of ITRS PD Needs • Analog layout synthesis and reuse • Layout-BIST synergies for UDSM fault models • New paradigms for global signaling, synchronization and system-level interconnect • Modeling and simulation • Mitigation of increased process variability and non-recurring costs in mask and foundry flows • Multi-(Vdd, Vt, tox, biasing) performance optimization • …

21. Anatomy of Recent PD Literature • (1) placement / partitioning • (2) routing / global routing / wireplanning • (3) interconnect tree (buffered / Steiner / RAT / …) construction • (4) floorplanning / block packing / macro-cell placement • (5) performance optimization (sizing, etc.) • (6) RTL-down methodology / flow • (7) clock • (8) power • (9) custom layout (transistor-level / migration / compaction) • (10) analog • (11) manufacturability / yield • (12) logical-physical interactions • (13) signal integrity • Table: DAC (Y) / ICCAD (Y) / ISPD (Y+1), in Y = 1996, …, 2001

22. Distribution of Physical Design Papers Among 13 Topics Where are the ITRS challenges?

23. Dissimilarity by Compression  • ((ISPD97 + CADT).gz – CADT.gz) / ISPD97.gz • ((ISPD97 + ISPD02).gz – ISPD02.gz) / ISPD97.gz = 0.78

24. Outline • What we need • ITRS challenges, logical/circuit/physical needs • SRC needs • What we do • Allocation of effort, versus needs and resources • Harmful practices • What we need to do • Coopetition • Shared red bricks • What we need to do, II • A top-10 list

25. What Is Going On Here? • Three pernicious phenomena • (1) Long lead times and latencies: formulation to solution to technology transfer to marketplace … • (2) High startup costs and other barriers to entry in research • (3) Research field recreates itself in its own image

26. It’s Not A Moving Target • PD roadmap has been static • Convergent integration of logic, timing, spatial embedding • Unification of incremental timing/SI closure with PA backplane • Methodology and routing contexts • Some references • NTRS/ITRS since 1994 • 1995 Sematech CHDS specification • L. Scheffer, PDW96: “We’re Solving the Wrong Problems” • Other examples listed in paper

27. Hello?

28. Hello??

29. Too Much Back-Filling? • Practice of putting well-known and already commercialized techniques into the public literature • Some impact on IP and research efficiency, but only if there is adequate transfer of the resulting technology! • Standard planning framework, next-generation detailed routers, etc. are better left to industry • Academia would benefit from more industry-strength shared research infrastructures

30. What Should Be Novel in Research? • Novelty in formulation, or novelty in optimization? • Claim: PD is focusing more on “novel” problem statements, while only transferring or reusing core optimization techniques • 15+ years ago: PD was the source of simulated annealing, LP relaxation/rounding, hierarchical routing, etc. • Past decade: mostly transferring methods (e.g., multilevel (PDW96, DAC97)) • Again: “We’re solving the wrong problems” • Cf. “packing obsession” in floorplanning literature • Shortage of optimization tools • No shortage of problems

31. Outline • What we need • ITRS challenges, logical/circuit/physical needs • SRC needs • What we do • Allocation of effort, versus needs and resources • Harmful practices • What we need to do • Mindset Change #1: Coopetition • Mindset Change #2: Shared red bricks • What we need to do, II • A top-10 list

32. Vision: Improved Design Technology Productivity • MARCO GSRC Calibrating Achievable Design theme • http://vlsicad.ucsd.edu/GSRC/ • Improved design technology planning (“specify”): • What will the design problem look like? What do we need to solve? • Improved execution (“develop”): • How can we quickly (TTM) develop the right design technology (QOR)? • Reusable, commodity, foundation CAD-IP (+ new publication standards) • Improved measurement (“measure and improve” ): • Did we solve the problem (QOR)? Did the design process improve? Did we increase the envelope of achievable design? • Design tool/process metrics, design process instrumentation and continuous process improvement • Ethos of “coopetition” (cooperation among competitors)

33. “Living ITRS” Framework

34. CAD-IP Reuse • Rapid development and evaluation of fundamental algorithm technology, via CAD-IP reuse • CAD-IP = Data models and benchmarks • context descriptions and use models • testcases and good solutions • CAD-IP = Algorithms and algorithm analyses • mathematical formulations • comparison and evaluation methodologies for algorithms • executables and source code of implementations • leading-edge performance results • CAD-IP = Traditional (paper-based) publications

35. MARCO GSRC Bookshelf: A Repository for CAD-IP • New element of VLSI CAD culture • “Community memory” currently centered in back-end • data models, algorithms, implementations • repository for open-source “foundation CAD-IP” • Publication medium that supports efficient CAD R&D • benchmarks, performance results • algorithm descriptions and analyses • quality implementations (e.g., open-source UCLA PDTools) • Enables comparisons to identify best approaches • Enables communication by industry of use models, problem formulations • http://gigascale.org/bookshelf/ • Have you open-sourced your code in the Bookshelf?

36. Outline • What we need • ITRS challenges, logical/circuit/physical needs • SRC needs • What we do • Allocation of effort, versus needs and resources • Harmful practices • What we need to do • Mindset Change #1: Coopetition • Mindset Change #2: Shared red bricks • What we need to do, II • A top-10 list

37. What Is A “Red Brick” ? • Red Brick = ITRS Technology Requirement with no known solution • Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment

38. Another ITRS Analogy • ITRS technologies are like parts of the car • Every one takes the “engine” point of view when it defines its requirements • “Why, you may take the most gallant sailor, the most intrepid airman, the most audacious soldier, put them at a table together – what do you get? The sum of their fears.” - Winston Churchill • All parts must work together to make the car go smoothly • Need global optimization of resource allocations with respect to requirements  shared red bricks

39. “Design-Manufacturing Integration” • 2001 ITRS Design Chapter: “Manufacturing Integration” = one of five Cross-Cutting Challenges • Goal: share red bricks with other ITRS technologies • Lithography CD variability requirement new Design techniques that can better handle variability • Mask data volume requirement  solved by Design-Mfg interfaces and flows that pass functional requirements, verification knowledge to mask writing and inspection • ATE cost and speed red bricks  solved by DFT, BIST/BOST techniques for high-speed I/O, signal integrity, analog/MS • Does “X initiative” have as much impact as copper?

40. Example Red Brick: Dielectric Permittivity Do we really need this? Bulk and effective dielectric constants Porous low-k requires alternative planarization solutions Cu at all nodes - conformal barriers C. Case, BOC Edwards – ITRS-2001

41. 100nm ITRS Requirement WITH Cu Barrier 70nm ITRS Requirement WITH Cu Barrier Example Red Brick: Copper Resistivity Is this even possible? Conductor resistivity increases expected to appear around 100 nm linewidth - will impact intermediate wiring first - ~ 2006 Courtesy of SEMATECH C. Case, BOC Edwards – ITRS-2001

42. PD + PIDS (Devices/Structures) • CV/I trend (17% per year improvement) = “constraint” • Huge increase in subthreshold Ioff • Room temperature: increases from 0.01 uA/um in 2001 to 10 uA/um at end of ITRS (22nm node) • At operating temperatures (100 – 125 deg C), increase by 15 - 40x • Standby power challenge • Manage multi-Vt, multi-Vdd, multi-Tox in same core • Aggressive substrate biasing • Constant-throughput power minimization • Modeling and controls passed to operating system and applications • Aggressive reduction of Tox • Physical Tox thickness < 1.4nm (down to 1.0nm) starting in 2001, even if high-k gate dielectrics arrive in 2004 • Variability challenge: “10%” < one atomic monolayer

43. PD + Lithography • 10% CD uniformity is a red brick today • 10% < 1 atomic monolayer at end of ITRS • This year: Lithography, PIDS, FEP agreed to raise CD uniformity requirement to 15% (but still a red brick) • Design for variability • Novel circuit topologies • Circuit optimization (conflict between slack minimization and guardbanding of quadratically increasing delay sensitivity) • Centering and design for $/wafer • Design for when devices, interconnects no longer 100% guaranteed correct? • Potentially huge savings in manufacturing, verification, test costs

44. PD + Assembly and Packaging • Goal: cost control ($0.07/pin, $2 package, …) • “Grand Challenge” for A&P: work with Design to develop die-package co-analysis, co-optimization tools • Bump/pad counts scale with chip area only • Effective bump pitch roughly constant at 300um • MPU pad counts flat from 2001-2005, but chip current draw increases 64% • IR drop control challenge • Metal requirements explode with Ichip and wiring resistance • Power challenge • 50 W/cm2 limit for forced-air cooling; MPU area becomes flat because power budget is flat • More control (e.g., dynamic frequency and supply scaling) given to OS and application • Long-term: Peltier-type thermoelectric cooling, …

45. PD + Manufacturing Test • High-speed interfaces (networking, memory I/O) • Frequencies on same scale as overall tester timing accuracy • Heterogeneous SOC design • Test reuse • Integration of distinct test technologies within single device • Analog/mixed-signal test • Reliability screens failing • Burn-in screening not practical with lower Vdd, higher power budgets  overkill impact on yield • Design challenges: DFT, BIST  PD IS in the loop! • Analog/mixed-signal • Signal integrity and advanced fault models • BIST for single-event upsets (in logic as well as memory) • Reliability-related fault tolerance

46. How to Share Red Bricks • Cost is the biggest missing link within the ITRS • Manufacturing cost (silicon cost per transistor) • Manufacturing NRE cost (mask, probe card, …) • Design NRE cost (engineers, tools, integration, …) • Test cost • Technology development cost who should solve a given red brick wall? • Return On Investment (ROI) = Value / Cost • Value needs to be defined (“design quality”, “time-to-market”) • Understanding cost and ROI allows sensible sharing of red bricks across industries • PD is at the heart of these potential partnerships • PD is in the best position to share R&D investment!

47. Outline • What we need • ITRS challenges, logical/circuit/physical needs • SRC needs • What we do • Allocation of effort, versus needs and resources • Harmful practices • What we need to do • Coopetition • Shared red bricks • What we need to do, II • A top-10 list

48. A Top-10 List • (0) Sensible unifications to co-optimize global signaling, manufacturability enhancement, and clock/test/power distribution • (1) Fundamental new combinatorial optimization technologies (and possibly geometry engines) for future constraint-dominated layout regimes • (2) New decomposition schemes for physical design • (3) Global routing that is truly path-timing aware, truly combinatorial, and able to invoke “atomistic” interconnect synthesis • (4) In-context layout synthesis that maximizes process window while meeting electrical (functional) spec

49. A Top-10 List • (5) Efficient analog and mixed-signal layout synthesis • (6) Methods for synchronization and global signaling at multi-GHz or –Gbps, extending to system-level • (7) Analysis, modeling and simulation methods that are tied more closely to PD syntheses, and that adapt to resource and accuracy and fidelity constraints • (8) Revival of platform-specific (parallel, distributed, hardware-accelerated) algorithm implementations • (9) Mindset changes, including a culture of “duplicating, deconstructing and debunking”

50. Conclusions • PD roadmap is static and well-known • There is a mismatch with semiconductor industry needs, and basic problems remain untouched • We in academia should not overemphasize back-filling and formulation over innovation and optimization • As a community, we must become more mature and efficient in how we prioritize research directions and use our human resources • The scope of PD must expand: up, down, out, back – even as renewed focus is placed on basic optimization technology • PD is at the heart of shared red bricks – we should and must seize this opportunity for new R&D investment