ROAD: Routability Analysis & Diagnosis Based on SAT Techniques

ROAD: Routability Analysis & Diagnosis Based on SAT Techniques SLIP 2018 (Published) ISPD 2019 (Accepted) CK Cheng CSE Department UC San Diego

Physical Design getting Harder • Keep Scaling Technologies • Design Rule Complexity Rising More and more complex of Place & Routing in Physical Design !!

Introduction: Design Procedure of Physical Design • Efforts to improve pin accessibility • Failure to produce routable (or routed) design in each step • loop-back of PD procedure • undesired additional design cost Gate Netlist • BEOL-aware cell layout design • routing-driven placement • Migration, congestion Placement Routable? by (1) or (2) No Yes • New detailed routing algorithm • pin-access planning Routing IF Unroutable… • DRC violations • manufacturability ECO (Engineering Change Order) Routed Layout

Introduction : Design Rules • Performance Design Rule • Interconnect parasites • Electronic migration • Geometry Design Rules • Minimum area rule • End of line spacing rule: minimal distance between two ends of wire segments • Via rules: minimal spacing between two vias, and stacked via rule. • Design Processes to mitigate Process-Design Gap • LELE (litho-etch-litho-etch) • SADP (self-aligned double patterning) • SAQP (self-aligned quadruple patterning)

Introduction : Next Gen Litho. (EUV) Resource Requirement https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography

Design Rule-Correct Routability Analysis ILP: Optimal but 1048s (~18min) ! Gate Netlist Placement Given Pin-Layout SAT : Not Optimized but 2s !!!!! Routable? SAT Method  Quick “go/no-go” Decision

What is SAT (Boolean Satisfiability) ? • SAT (Boolean Satisfiability) • Find an assignment so that the formula is true (1) (Satisfiable) , or prove that no such assignment exists (0) (Unsatisfiable) • Usually, Product of Sum (i.e. CNF) is normal representation for SAT formula Truth Table Sum of Product (DNF) Product of Sum (CNF) Equivalent Representations

SAT-Based Framework for Routability Analysis • ILP-based routability optimization • SAT-based routability analysis Our Proposed Framework Routability Analysis Flow Testcase (i.e., Switchbox) Generation • Inputs • #Vertical and Horizontal Tracks • Pin Density Logic Simplification ILP Patterns per ILP Formula SAT-Friendly ILP Formulation • Switchboxes • 3D Routing Graph • Source-Sink Definition Logic Minimizer Espresso [26] ILP-to-SAT Conversion ILP Inputfiles Solvers ILP Solver CPLEX [27] Reduced SAT Inputfiles SAT Solver plingeling [28] SAT Inputfiles Results of Routability Analysis ILP Result: Routing Feasibility, Wirelength, Metal Cost, etc. SAT Result: Routing Feasibility, SAT Solution if Satisfiable by SAT by ILP [27] IBM ILOG CPLEX, http://www.ilog.com/products/cplex/. [28] plingeling, Multi-Threading SAT Solver, http://fmv.jku.at/lingeling/.

Next Step : Routability Diagnosis and Estimation • Conflict Diagnosis in Unroutable Case using SAT Technique • Exact Location of Conflict  Fast Trouble-shooting for Designer • Exact Conflict Relation  Guideline for Design Rule Manager • Routability Quantification • Estimate the routing possibility upon given switch-box  “go/no-go” decision for revision of switch-box

RODE : ROutability Diagnosis & Estimation Routability Analysis Using SAT Formulation Estimation Diagnosis Unroutable Layout Node : U (variable) MUS MUS Extraction(Minimal Unsatisfiable Subset) Clause Minimization Ub BCP Iteration Edge : D (clause) Initial Propagation (Geometric Information of Switch-Box) Conflict Region PIG Us Decision (DLS)(Decision with Longest-Path Search) Up Propagation (PTA/PFA) (Propagation with True/False Assignment) No Conflict? Yes DAG : H(U,D) Conflict Information (Conflict Geometry / Design Rule)

RODE : Notation & Pin-layout Configuration M1 in G M2 in G 2 1 2 1 2 1 2 2 M3 in G M4 in G Outer-Pin Connection Power Rail PIN #1 V-Track H-Track 1 Grid

Proposed SAT Formulation Diagram • The Multi-commodity network flow formulation (F) • Conditional Design Rule (D) Conditional Design Rules (D) 1. End-of-Line Space Rule (EOL) 2. Minimum Area Rule (MAR) 3. Via Rule (VR) Commodity Flow Conservation (CFC) Exclusiveness Use of Vertex (EUV) Edge Assignment (EA) Metal Segment (MS) Geometry Variable (GV) Flow Formulation (F)

SAT Formulation – Flow Formulation (F) • Commodity Flow Conservation (CFC) • Vertex is not a source or sink • Vertex is a source or sink 1) Only one incoming/outgoing pair is allowable for all commodities. 2) This commodity don’t use this vertex. • Exactly-One (EO) Constraint

SAT Formulation – Flow Formulation (F) • Exclusiveness Use of Vertex (EUV) • Vertex is not a source or sink • Vertex is a source or sink 1) Only n net flow can be assigned if a certain edge is occupied by the n net 2) This net don’t use this vertex. • At-Most-One (AMO) Net Constraint

SAT Formulation – Flow Formulation (F) • Edge Assignment (EA) • Metal Segment (and Exclusiveness Use of Edge) (MS) • AMO Constraint Logical Imply. : edge is used by n net if m commodity of n net use this edge  It requires for multi-commodity flow

SAT Formulation – Design Rule Formulation (D) • Geometric Variable (GV) • End-of-Line indicator of each vertex for geometric conditional design rule.

SAT Formulation – Design Rule Formulation (D) • Minimum Area Rule (MAR) • A metal segment must cover at least three vertices (AMO) True Table  Karnaugh Map  CNF conversion by Espresso (Logic Minimizer) No Violation Violation

SAT Formulation – Design Rule Formulation (D) • End-of-Line (EOL) Space Rule • The minimum distance between tips must be larger than 2 Manhattan distance (AMO) Violation Violation No Violation

SAT Formulation – Design Rule Formulation (D) • Via Rule (VR) • The distance between two vias should be larger sqrt(2) Euclidean Distance (AMO) No Violation Violation

SAT Formulation – Design Rules are always mixed • Mixed Design Rule Violation VIA(M1↔M2) VIA(M2↔M3) No Violation Violation No Violation (a) Violation (VR OK, EOL Fail) No Violation (b) Violation (VR OK, EOL Fail)

Design Rule-Correct Routability Analysis • Flow Feasibility (F) • Conjunction of each subsets • Design Rule Formulation (D) • Design Rule-correct Routability ( R ) • L : Layout Structure Map  the geometry information of the switch box

(1) Minimal Unsatisfiable Subset (MUS)

(2) Boolean Constraint Propagation (BCP) • BCP • The procedure is based on Unit Clauses • If a set of clauses contains the unit clause , the otherclauses are simplified by the application of the two following rules • Every clause containing is removed • In every clause that contains this literal is deleted * BCP Iteration Example Clause set: https://en.wikipedia.org/wiki/Unit_propagation

(3) Partial Implication Graph (PIG) • PIG in Our Framework • Directed Acyclic Graph which Nodes are Variables, Edges are Clauses. • The implication relation between variable assignment from constraint clause PIG of the propagation a Clause set: c d https://en.wikipedia.org/wiki/Unit_propagation

After Initial Propagation 0 1 • The intersection range between GV and MS  Estimated Conflict Range 2 3 4 5 Power Rail 6 • #V_Tracks= 9 • #H_Tracks= 13 • PinDensity= 100% • 14 Pins: 0-13 • 8 Outer Pins: 14-21 • 10 Nets: {1 7 18}, {2 6 20}, {3 10}, {13 19}, {9 12}, {4 17}, {8 14}, {0 16}, {5, 15}, {11 21} 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 Estimated Conflict Region 10 13 8 11 5 6 0 1 2 7 9 12 4 3

DLS (Decision with Longest-path Search) 0 1 • Longest-path search is most comprehensive explanation about failure • Via Position / Direction of Element are determined at DLS phase 2 3 4 5 Selected ! 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 Blocked via (M1 ↔ M2) Conflict @ 4th Conflict @ 2nd Conflict @ 1st 10 10 10 13 13 13 8 8 8 11 11 11 5 5 5 6 6 6 0 0 0 1 1 1 2 2 2 7 7 7 9 9 9 12 12 12 4 4 4 3 3 3

PTA (Propagation with True Assignment) (1) • BCP propagation with True Assignment (Us) (2) (3) (3) (2) (1)

PTA (Propagation with True Assignment) 0 1 • PTA Result of #1 VIA @ 9_13_100 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 10 13 8 11 5 6 0 Blocked via (M1 ↔ M2) 1 2 7 9 12 4 3 Blocked via (M2 ↔ M3) Assigned via (M1 ↔ M2)

PFA (Propagation with False Assignment) • BCP propagation with False Assignment (Us) • Via-to-via spacing / Stacked – Via / Vias in same pin / element with direction against PTA Blocked via Blocked in-layer element

PFA (Propagation with False Assignment) 0 1 • PFA Result of #1 VIA @ 9_13_100 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 10 13 8 11 5 6 0 Blocked via (M1 ↔ M2) 1 2 7 9 12 4 3 Blocked via (M2 ↔ M3) Assigned via (M1 ↔ M2) Blocked in-layer element

Diagnosis result of 9_13_100 0 1 • 4th via @ PFA phase  Conflict encounter ! 2 3 4 Blocked via (M1 ↔ M2) 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 CONFLICT Information • Geometry : (Pin0) ↔ (7,10,1) • Design Rule : CFC ↔ VR Rule 10 13 8 11 5 6 0 1 2 7 9 12 4 3

Routability Estimation using Practical Pin-layout • Routability Estimation using Automated Generated Pin-layout • Rent’s Rule  Practical Pin-layout • Routability Quantification  Useful Information to Designer With One Row of Pins With Two Row of Pins

Routability Estimation – Unroutability Trend • Unroutability Comparison vs. the number of pin row - - - - -

Routability Diagnosis – Root Causes • The Root causes of routing failure • Conflict Pin-shape (CP) : Pin-Accessibility Problem! • Simple-CP : Intrinsic Pattern in given Pin-layout • Propagated-CP : Simple-CP appears after some propagations • Routing Congestion • The lack of routing resources such as #Track and #Layer

Unroutable layout Classification – Simple-CP • Simple-CP with 3-3-n-3-3 pattern • #V_Tracks= 9 , #H_Tracks= 13 • PinDensity= 100% • 14 Pins: 0-13 • 8 Outer Pins: 14-21 • 10 Nets: {1 7 18}, {2 6 20}, {3 10}, {13 19}, {9 12}, {4 17}, {8 14}, {0 16}, {5, 15}, {11 21} Unroutable Pin-shape Pattern 3 – 3 – n – 3 – 3 10 13 8 11 5 6 0 1 2 7 9 12 4 3

Unroutable layout Classification – Propagated-CP 0 11 11 5 5 13 13 7 7 4 4 3 3 1 • Propagated-CP : Main Concern of Pin-accessibility Why designer don’t change Pin-shape? 2 3 4 5 6 7 8 9 10 11 12 11 10 9 0 1 2 3 4 5 6 7 8 1 1 8 8 6 6 2 2 0 0 10 10 12 12 9 9 • #V_Tracks= 12, #H_Tracks= 13 • PinDensity= 70% • 14 Pins: 0-13 • 9 Outer Pins: 14-22 • 10 Nets: {2 13 14}, {10 12 15}, {4 8 21}, {0 22}, {6 20}, {3 16}, {7 17}, {5 11}, {9 19}, {1 18} Unroutable Pin-shape Pattern 3 – 3 – 3

Unroutable layout Classification – Routing Congestion • Routing Congestion : Technology Limitation Identification! 12 13 14 11 1 2 3 4 5 6 7 8 9 10 0 • #V_Tracks= 15, #H_Tracks= 7, PinDensity= 90% • 12 Pins: 0-11 • 8 Outer Pins: 12-19 • 9 Nets: {2 11 14}, {5 8 13}, {3 15}, {6 12}, {9 16}, {1 4}, {7 19}, {0 17}, {10 18} 0 1 2 3 4 5 6 All tracks are occupied / blocked !! (a) 1 1 1 10 10 10 3 3 3 2 2 2 8 8 8 9 9 9 0 0 0 7 7 7 4 4 4 5 5 5 11 11 11 6 6 6

Routability Diagnosis Experimental Statistics • Total Diagnosis Time • MUS Extraction Time + Decision & Propagation Time • Diagnosis Performance (Complexity and Execution Time) depends on the root causes of routing failure • CP Pattern Case is less than 30 seconds to get the result. • Routing Congestion Case is relatively hard to find the failure causes.

Routability Diagnosis – Root Cause Configuration • Same Grid Number with different number of pins row

Publications with This Project • Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng. “Fast and Precise Routability Analysis with Conditional Design Rules”. SLIP 2018 • Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bil Lin and Chung-Kuan Cheng. “ RODE: Efficient Routability Diagnosis and Estimation Framework Based on SAT Techniques”. ISPD 2019 (Will Published at 2019/April) • Journal Extension will be prepared soon.

SAT Solving Performance Improvement

CSP to SAT • Constraint Optimization • Constraint Simplification • ABC (AIGs) • MIG Techniques • Converting Encoding Method • Direct Encoding (Sparse Encoding) • Ordering Encoding • Log Encoding CSP (Constraint Satisfaction Problem) SAT (Boolean Satisfiability) • CNF Optimization • Preprocessing (BCP) • Encoding Techniques for EO / AMO

ROAD Improvement (1) – Super Outer Node (SON) • Super Outer Node : Representation Simplifying Conventional Super Node Super Outer Node (SON)

ROAD Improvement (2) – Encoding Techniques For AMO/EO

ROAD Improvement (3) – Preprocessing : BCP • BCP • The procedure is based on Unit Clauses • If a set of clauses contains the unit clause , the otherclauses are simplified by the application of the two following rules • Every clause containing is removed • In every clause that contains this literal is deleted * BCP Iteration Example Clause set:

Simplified SAT Formulation • In Largest Case (20x19 x 90% Density) of SLIP 2018 • 29.4% of #Variable / 0.9% of #Literal / 0.7% of #Clause are acquired using simplification techniques ( SON , Commander Encoding for AMO/EO , BCP Preprocessing ) • #Net = Number of Net , #Pin = Number of Pin, #OTP = Number of outer directional pin

More Future Work • Utilizing Framework • Photonic Interconnection Design based on Waveguide technology • Utilizing Diagnosis : Pin-shape Pattern Conflict • Machine Learning can be applicable by Pattern Training • Placement Refinement Technique Suggestion • Utilizing Diagnosis : Routing Resource Conflict Case • Identifying Technology Limitation • Pin-Shape Design (Pin also the variable, not given) • Optimized SAT Solution using SMT Technique • Minimum Wire/Metal Cost based on SAT

Appendix

M1 Routing Difficulty • Cell Design Using M1 (Currently, Bi-Directional)

ROAD: Routability Analysis & Diagnosis Based on SAT Techniques