Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices

1. Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices Andrzej Krasniewski Institute of Telecommunications WARSAW UNIVERSITY OF TECHNOLOGY

2. Increasingly more problems with timing of ICs because of • larger size and complexity • higher clock frequency • new phenomena in submicron technologies If you look for a single fault model, this should be some kind of delay model [T.M. Mak (Intel), panel discussion at IOLTS’03] MOTIVATION Why delay faults (and not static faults)?

3. some timing problems caused by effects specific for the system environment(noise/interference) only a small fraction of all possible inteconnection patterns can be exercised by the manufacturer Xilinx offers testing FPGA devices programmed with user-defined function (reduction of test costs by 80%) [I. Bolsens (Xilinx), keynote at IOLTS’03] MOTIVATION (cont.) Why testing user-configured device (and not relying on manufacturer’s test)?

4. extremely difficult to generate deterministic patterns that account for different reasons for delay faults [Krstic&Liou, ITC’01] for FPGAs, BIST at no circuitry overhead or performance penalty Random testing is likely to be a preferred test strategy for FPGA delay faults MOTIVATION (cont.) Why evaluation of testability (and not test pattern generation)?

5. PROBLEM Analysis of timing-related faults in FPGAs - not easy to handle using “conventional” methods conventional circuits (simple gates) FPGAs (LUT-based) static faults dynamic faults (delay faults) ??? Specific features of FPGAs e.g. nonexistence of controlling values for many inputs to basic logic components - LUTs

6. OUTLINE • Propagation delays and paths delay faults in FPGAs • Evaluation of testability of path delay faults – key factors • Observations and practical guidelines testability measures type of tests fault model (set of target faults) restrictions on the set of input pairs

7. Active Logic Component (ALC):after programming, output depends on two or more inputs original path ALC-based model PATH DELAYS IN FPGAs

8. network of ALCs - model of a combinational section of an FPGA with aminimal number of components necessary for an analysis of path delays PATH DELAYS IN FPGAs (cont.) ASSUMPTIONS • delays are assigned to both ALCs and connections • delays of ALCs and connections may depend on the polarity of signal transitions • delays of programmable ALCs may depend on their specific user-defined functions [Girard et al., IOLTS’03] • for a multiple-destination connection, different delays maybe assignedto its different branches

9. path delay (fault) logical path logical path = path (physical) + path transition pattern e.g. cdfk logical path must comply with ALC functions e.g. cdfkis not a logical path is apseudological path feasible logical path path transition pattern produced by some functional input pair LOGICAL PATHS & CORRESPONDING FAULTS

10. The speed of thenetwork can only be affected by propagation delays (delay faults) associated with delay-essential logical paths [Krasniewski, DDECS’03] LOGICAL PATHS & CORRESPONDING FAULTS (cont.) disturbances in the fabrication set of feasible logical paths logical path unknown delay assignment DA sensitizable (true) under some DA YES NO never determines the speed of the network irredundant path redundant path

11. all pseudological and logical paths all logical paths feasible irredundant delay-essential Ideal fault modelset of target faults associated with delay-essential paths No knowledge of network timing is necessary to identify the set of delay-essential paths examination of s-sensitizability of multipaths is necessary LOGICAL PATHS & CORRESPONDING FAULTS (cont.)

12. OUTLINE • Propagation delays and paths delay faults in FPGAs • Evaluation of testability of path delay faults – key factors • Observations and practical guidelines testability measures type of tests fault model (set of target faults) restrictions on the set of input pairs

13. TESTABILITY EVALUATION susceptability of network to testing efficiency of test procedure EVALUATION OF TESTABILITY OF DELAY FAULTS TESTABILITY MEASURES TYPE OF TESTS TEST SEQUENCE DEFINING TEST. MEASURES FOR PHYSICAL PATHS RESTRICTIONS ON INPUT SET SET OF TARGET FAULTS class of logical paths set of critical paths MODEL OF NETWORK AND PROPAGATION DELAYS specific for FPGAs

14. TYPES OF TESTS weak non-robust (WNR) strong non-robust (SNR) robust (R) Examples of testability measures: fault testability for robust tests (R-testability) fault coverage for weak non-robust tests (WNR-coverage) TESTABILITY MEASURES & TYPES OF TESTS TESTABILITY MEASURES susceptbility of network to testingfault testability quality of test sequence fault coverage

15. TESTABILITY MEASURES TESTABILITY EVALUATION TYPE OF TESTS susceptability of network to testing TEST SEQUENCE efficiency of test procedure DEFINING TEST. MEASURES FOR PHYSICAL PATHS RESTRICTIONS ON INPUT SET SET OF TARGET FAULTS class of logical paths set of critical paths MODEL OF NETWORK AND PROPAGATION DELAYS specific for FPGAs EVALUATION OF TESTABILITY OF DELAY FAULTS

16. defined by a class of logical paths all pseudological and logical paths all logical paths feasible irredundant delay-essential SNR-testable R-testable WNR-testable SET OF TARGET FAULTS

17. SET OF TARGET FAULTSSELECTION - EXAMPLE 19 physical paths 102 pseudological paths 90 logical paths

18. SET OF TARGET FAULTSSELECTION - EXAMPLE „Exact” valuesof testability measuresreasonablywell approximated ifthe set of target faults associated with irredundant and SNR-testable logical paths

19. SET OF TARGET FAULTS – CRITICAL PATHS criticalpaths = longest paths, identified by structural or timing anlysis critical (physical) path more logical paths sensitization requirements more difficult to satisfy  lower values of testability measures

20. TESTABILITY MEASURES TESTABILITY EVALUATION TYPE OF TESTS susceptability of network to testing TEST SEQUENCE efficiency of test procedure DEFINING TEST. MEASURES FOR PHYSICAL PATHS RESTRICTIONS ON INPUT SET SET OF TARGET FAULTS class of logical paths set of critical paths MODEL OF NETWORK AND PROPAGATION DELAYS specific for FPGAs EVALUATION OF TESTABILITY OF DELAY FAULTS

21. TESTABILITY MEASURES DEFINED FOR LOGICAL PATHS delay faults logical paths of a certain class  a physical paths with many logical paths (of a certain class) has a significantly higher impact on testability measures than a physical path with few logical paths TESTABILITY MEASURES DEFINED FOR PHYSICAL PATHS simplest idea: a physical path  has a certain testability-oriented property, e.g. is delay-essential or is R-covered by some test sequence, if at least one logical path associated with  has this property TESTABILITY MEASURES FOR PHYSICAL PATHS

22. TESTABILITY MEASURES FOR PHYSICAL PATHS

23. TESTABILITY MEASURES TESTABILITY EVALUATION TYPE OF TESTS susceptability of network to testing TEST SEQUENCE efficiency of test procedure DEFINING TEST. MEASURES FOR PHYSICAL PATHS RESTRICTIONS ON INPUT SET SET OF TARGET FAULTS class of logical paths set of critical paths MODEL OF NETWORK AND PROPAGATION DELAYS specific for FPGAs EVALUATION OF TESTABILITY OF DELAY FAULTS

24. network of ALCs CLK CLK restricted set of input pairs- system function- sequential nature of subcircuit Restrictions on the set of input pairs affect the relevant classes of logical paths (sets of target faults) [Krasniewski, IOLTS’03] RESTRICTIONS ON INPUT SET

25. all pseudological and logical paths all logical paths feasible restrictions on the set of input pairs apply irredundant delay-essential SNR-testable R-testable WNR-testable Restrictions on the set of input pairs must be accounted for when calculating testability measures RESTRICTIONS ON INPUT SET

26. OUTLINE • Propagation delays and paths delay faults in FPGAs • Evaluation of testability of path delay faults – key factors • Observations and practical guidelines testability measures type of tests fault model (set of target faults) restrictions on the set of input pairs

27. OBSERVATIONS AND PRACTICAL GUIDELINES The values of path delay fault testability measures strongly depend on assumptions taken when calculating these values Example network Coverage of the path delay faults, calculated for the considered test sequence varies from 13.3 % (6.3 %) coverage of faults corresponding to all logical paths (pseudological and logical paths) by R-tests to 82.4 % coverage of faults corresponding to SNR-testable physical paths by WNR-tests

28. Selection of the class of logical paths that defines the fault model poses an accuracy-complexity trade-off exact values, corresponding to the set of delay-essential logical paths - very difficult to calculate easy-to-calculate approximations - unacceptably inaccurate sets of target faults corresponding to irredundant and SNR-testable logical paths provide reasonably accurate estimates • Selection of critical paths only - questionable reasonable if the set of critical paths is a small subset of the set of all paths - usually not the case for speed-optimized circuits OBSERVATIONS AND PRACTICAL GUIDELINES (cont.)

29. Defining testability measures for physical paths - attractive especially in the case when the rising and falling delays of individual components can be assumed equal or, at least, not significantly different • Restrictions on the set of vector pairs that occur at the input of the network in normal operation should be considered when defining the set of target faults especiallyin the case when the fault coverage is calculated for a test sequence that has been developed taking into account these restrictions OBSERVATIONS AND PRACTICAL GUIDELINES (cont.)

30. Evaluation of testability of delay faults foruser-configured FPGAs- difficult, both conceptually and computationally Whenever the value of any measure of path delay fault testability for an FPGA is reported, a detailed explanation on what is reported should be given Obvious? NO! In many publications, the presented values are claimed to represent “the coverage of path delay faults by robust tests” or sometimes even “the coverage of path delay faults” uncertainty about the meaning of the results (test quality) examplecoverage of 50% of path delay faults- excellent test quality ifR-coverage of delay-essential logical paths- poor test effort if coverage of R-testable logical paths by WNR tests CONCLUSION