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A 40-Gb/s Decision Circuit in 90-nm CMOS T. Chalvatzis 1 , K. H. K. Yau 1 , P. Schvan 2 , M.-T. Yang 3 and S.

A 40-Gb/s Decision Circuit in 90-nm CMOS T. Chalvatzis 1 , K. H. K. Yau 1 , P. Schvan 2 , M.-T. Yang 3 and S. P. Voinigescu 1 1 Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada 2 Nortel Networks, Ottawa, Canada 3 TSMC, Hsin-Chu, Taiwan.

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A 40-Gb/s Decision Circuit in 90-nm CMOS T. Chalvatzis 1 , K. H. K. Yau 1 , P. Schvan 2 , M.-T. Yang 3 and S.

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  1. A 40-Gb/s Decision Circuit in 90-nm CMOS • T. Chalvatzis1, K. H. K. Yau1, P. Schvan2, • M.-T. Yang3 and S. P. Voinigescu1 • 1Department of Electrical and Computer Engineering, • University of Toronto, Toronto, Canada • 2Nortel Networks, Ottawa, Canada • 3TSMC, Hsin-Chu, Taiwan

  2. Outline • Motivation • Decision Circuit Design • Measurement Results • Summary T. Chalvatzis, University of Toronto - ESSCIRC 2006

  3. Motivation • Low-power, high-speed blocks in CMOS for mm-wave A/D Conversion [Chalvatzis, et al., RFIC2006] • Low-power blocks for 40-Gb/s wireline and fiber-optic transceivers in CMOS T. Chalvatzis, University of Toronto - ESSCIRC 2006

  4. Decision Circuit Block Diagram • Two latches in Master-Slave configuration • Data and clock amplifiers as TIAs • Output driver buffers to 50Ω T. Chalvatzis, University of Toronto - ESSCIRC 2006

  5. Conventional Latch • Conventional CML latch requires 3 vertically stacked transistors • Standard 1.2V supply in 90nm • VDS too low for 40 Gb/s speed T. Chalvatzis, University of Toronto - ESSCIRC 2006

  6. Previous Work To operate from lower power supply (<1.2V) • Remove current sources [Kanda, et al., ISSCC2005] • -> Not sufficient for 40Gb/s operation • Transformer coupling for clock-to-data path [Kehrer, et al., CSICS2004] • -> Not broadband due to transformer T. Chalvatzis, University of Toronto - ESSCIRC 2006

  7. Proposed Latch • Bias at peak-fT current density IBIAS=Ipeak-fT/2=0.15mA/μm • High-VT devices on clock path • Low-VT devices on data path • For IBIAS=4.5mA and RL=40Ω: ΔV=9mAx40Ω=360mV • Total power consumption: 10.8 mW/latch T. Chalvatzis, University of Toronto - ESSCIRC 2006

  8. Retiming DFF – Schematic T. Chalvatzis, University of Toronto - ESSCIRC 2006

  9. Retiming DFF – Schematic • Clock must fully switch M1/M2 • VDS,M7/8 swings as low as VT (M1/M2) • Use high-VT for M1/M2 • VDS,M7/8=VDD-ΔVswing=VT=0.34V T. Chalvatzis, University of Toronto - ESSCIRC 2006

  10. TIA Design Methodology • Bias at min noise current density 0.15 mA/μm [Dickson, et al., JSSC Aug 2006] • p-MOS active load to increase gain at low VDD • Feedback inductor LF resonates out the capacitance at the TIA node • LF=500pH designed with two top metals for minimum footprint to obtain high SRF T. Chalvatzis, University of Toronto - ESSCIRC 2006

  11. TIA scaling to 65-nm CMOS TIA BW3dB=28GHz @ 3mA T. Chalvatzis, University of Toronto - ESSCIRC 2006

  12. Fabrication and measurement results of decision circuit T. Chalvatzis, University of Toronto - ESSCIRC 2006

  13. DFF DRIVER TIA CLOCKTREE Decision Circuit – Die Photo P=130mW @ VDD=1.2V Area=600x800μm2 Circuit fabricated in two different foundries T. Chalvatzis, University of Toronto - ESSCIRC 2006

  14. Retiming DFF – Test Setup • 40-Gb/s signal generated from 4x10Gb/s streams • Solid lines Data signals • Dashed lines Clock signals T. Chalvatzis, University of Toronto - ESSCIRC 2006

  15. Measurements at 30Gb/s Single-ended input with other input terminated to 50Ω Jitter from setup not de-embedded Input (top) Output (Bottom) FCLK=30GHz, Data Rate=30Gb/s, Trise=7ps JitterRMS,input=1.7ps JitterRMS,output=0.5ps T. Chalvatzis, University of Toronto - ESSCIRC 2006

  16. Measurements at 30Gb/s vs VDD, T Input (top) Output (Bottom) VDD=1V, T=25oC VDD=1.2V, T=100oC JitterRMS,input=1.7ps JitterRMS,input=1.4ps JitterRMS,output=0.7ps JitterRMS,output=1.0ps T. Chalvatzis, University of Toronto - ESSCIRC 2006

  17. Measurements at 37Gb/s and 40Gb/s Input (top) Output (Bottom) 37Gb/s @ 1.2V 40Gb/s @ 1.5V JitterRMS,input=1.292ps JitterRMS,input=1.403ps JitterRMS,output=1.149ps JitterRMS,output=1.396ps T. Chalvatzis, University of Toronto - ESSCIRC 2006

  18. Error-free 508-bit pattern Input (top), output (bottom) Measurements at 40Gb/s and 1.5V T. Chalvatzis, University of Toronto - ESSCIRC 2006

  19. Comparison of high-speed latches T. Chalvatzis, University of Toronto - ESSCIRC 2006

  20. Conclusion • 90-nm CMOS latch and retimer demonstrated at 37 Gb/s from 1.2 V and 40 Gb/s from 1.5 V supply • p-MOS device for low-noise TIA on data and clock path • Peak-fT bias and combination of low and high-VT devices in latch allows for 40-Gb/s retiming • 1.2-V operation at 40 Gb/s possible if clock path TIA replaced with a CML inverter chain with inductive peaking and source follower T. Chalvatzis, University of Toronto - ESSCIRC 2006

  21. Acknowledgements • Nortel Networks for funding support • STMicroelectronics and TSMC for chip fabrication • ECTI, OIT and CFI for equipment • NIT for lab access • CMC for CAD tools T. Chalvatzis, University of Toronto - ESSCIRC 2006

  22. Backup Slides T. Chalvatzis, University of Toronto - ESSCIRC 2006

  23. fT of LVT and HVT transistors T. Chalvatzis, University of Toronto - ESSCIRC 2006

  24. Input (top) – Output (bottom) 30Gb/s @ 1.2V and 60mV input (13-dB attenuation) Retiming with JitterRMS,input=1.9ps JitterRMS,output=1.7ps Measurements at 30Gb/s (min. input) T. Chalvatzis, University of Toronto - ESSCIRC 2006

  25. Input (bottom) – Output (top). 7.5Gb/s @ 1.2V Retiming with JitterRMS,input=4.2ps JitterRMS,output=2.6ps Measurements at 7.5Gb/s (Fclk/4) T. Chalvatzis, University of Toronto - ESSCIRC 2006

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