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Proposal for Lisbon group participation in the Tilecal electronics upgrade R&D

This proposal outlines the Lisbon group's interest in participating in the TileCal electronics upgrade activities in collaboration with CERN and IFIC Valencia. The main focus is on the development of firmware for link technology, processing, and control.

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Proposal for Lisbon group participation in the Tilecal electronics upgrade R&D

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  1. Proposal for Lisbon group participation in the Tilecal electronics upgrade R&D This proposal reflects our group’s interest to participate in the TileCal electronics upgrade activities from the earliest stages in collaboration with CERN and other institutions – in particular IFIC Valencia. Other upgrade related activities we already proposed to develop are not addressed in this presentation. Main interests: The activities included in WP3 of upgrade R&D proposalare of particular interest to our group since the expertise of the project team lies mainly in the development of firmware. We have started contacts with the IFIC group from Valencia, with the purpose of establishing a close collaboration in the future. In what concerns their participation in the R&D for the TileCal upgrade, the IFIC group is mainly involved in WP3 activities.

  2. WP3 R&D issues of interest: • WP3 b) • Link technology from front end. • Link technology to L1Calo trigger. • Firmware for links. • Firmware for processing. • Firmware for controller and Interface. • Back end architecture. • WP3 c) • ROD firmware. Given that we have contact with the GBT group at CERN, the firmware R&D issues related to the optical links technology and transmission protocol implementation stand out in the list of WP3 issues of interest for our group. Project will focus on firmware implementation in different FPGA technologies. Since the IFIC group is already evaluating the Virtex-5 ML555 board, both groups agreed that a possibility would be for Lisbon to use an Altera Stratix IV development platform.

  3. Equipment resources: • Available: • 1 digital oscilloscope 350 MHz (Agilent) • Several digital oscilloscopes 200 MHz (Tektronix) • 2 programmable signal generators (Agilent) • 1 data analyzer (Hamamatsu) • Several PC workstations • Access to advanced test and measurement • equipment at INESC* (Lisbon) • Requested: • FPGA evaluation board (Altera) • Up to date PC workstation • Samples of GBT hardware • Links, cables, transceivers, etc. • Research team: • José Augusto (Electronics) • Agostinho Gomes (Experimental Physics) • Guiomar Evans (Electronics) • José Silva (Experimental Physics) • Luís Gurriana (Experimental Physics) • Request of funds to hire 2 students • (1 graduate + 1 master) * INESC: Instituto de Engenharia de Sistemas e Computadores

  4. GBT & LIP Sophie Baron from CERN wroteusan email toinformabout: • We are thinkingaboutdesigning a set of 2 boardsequippedwithan FPGA to interface the and a data source. • As a supportgroup, wewouldprefertomaketheseboards in a waytheycouldbe re-usedbyexperiments • Do you plan, in thefuture, todesignyourown interface boardbetween GBT chips?, wouldyoubeinterested? Wouldone single GBT link beenoughforyouto test suchanarchitecture? whichform factor wouldyouprefer? • GBT firmware willbeavailable in January (1 monthdelayed) • Portugal Side : Jose & JoseWethinkthatthewayforustogois full cooperationwith Valencia and CERN, thatis, wethinkyou are in a muchbetter position to decide aboutwhat are theurgentneeds and thebetterboardstofullfillthem. • Here in Lisboa wedonthavethetools and thefundingtodevelopourownboards, so werelyonthosedeveloped in CERN or in Valencia. • we hope tohave a substantialamount of work done in theend of theyear in ordertogetthefundingnecessaryforextendingtheprojectforforthcomingyears.Our 1-year projectstarts in January, and in ourroadmapisthepromptacquisition of a FPGA developmentboard. Wewouldlikeyouropinionaboutwhatis more usefulfortheoverallgroup: tobuy a Xilinx board similar tothoseused in Valencia forthecurrentdevelopment; ortogofor a differentboard (Altera Stratix) toevaluateits performance limits. • Giventhis, weoffertodeveloppartiallyortotallysome firmware forinterfacingthe FPGA boardwewillacquiretothe GBT board(s) Sophie isplanningtodesign, and topush up theclocks in orderto test GBT speeds in thiscontext. • Weshouldcontact LIP people in odertostartthecollaborationas soon as possiblesincetheirprojectisstartingonJanuary ( butwealreadyhavestarted)

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