Efficient CMP-Aware Buffer Insertion and Wire Sizing

1. Simultaneous Buffer Insertion and Wire Sizing ConsideringSystematic CMP Variation and Random Leff Variation Lei He1, Andrew Kahng2, King Ho Tam1, Jinjun Xiong1 1Univ. of California, Los Angeles 2Blaze DFM, Inc. & Univ. of California, San Diego Sponsors: 1NSF CAREER, SRC, UC MICRO sponsored by Analog Devices, Fujitsu Lab., Intel and LSI Logic, IBM Faculty Partner Award; 2MARCO Gigascale System Research Center, NSF.

2. Existing Work on Variation-Aware Buffer Insertion • Buffer insertion for length variation [Khandelwal-ICCAD] • Variation sources from difference between estimated and actual wire length • Buffer insertion for process variation [Xiong-DATE] • Random Leff and interconnect width variations • Brute-force numerical manipulation of joint probability density functions (JPDFs), not efficient

3. Buffer Insertion and Wire Sizing (SBW) with Process Variations • Variations models • Leff – random variation • In reality, 50% systematic and 50% random • Interconnect RC – systematic variation due to Chemical Mechanical Planarization (CMP) • Random component of global interconnect variation on performance is insignificant in general • Efficient variation-aware algorithms • Table-based capacitance and fill insertion under CMP • Efficient pruning to deal with random variation

4. Outline • SBW and fill insertion (SBWF) under CMP variation • Modeling RC variation • CMP-aware SBW and fill insertion algorithm • Experiment: CMP-aware vs CMP-oblivious • Extension to Leff variation • Conclusion

5. Chemical Mechanical Planarization (CMP) • Metallization process • Etch trenches • Deposit Cu bulk • Cu removal by CMP • Dishing/Erosion • Loss of Cu thickness due to over-polishing • Fix: dummy fill insertion for more uniform Cu loss • Dummy fill insertion • Increase coupling cap

6. Chemical Mechanical Planarization (CMP) • Dishing and erosion lead to • Up to 31.7% increase in resistance • No change in capacitance • Fill insertion [He-SPIE] can lead to • 1.5x increase in coupling capacitance (Cc) • 2% increase in total capacitance (Cs) • Can be up to 10% increase if fill pattern is not optimized

7. RAT = 900ps C = 30fF RAT = 1200ps C = 2fF RAT = 2000ps C = 10fF RATopt ρ1 ρ6 Reff = 100Ω RAT = 2200ps C = 8fF ρ5 ρ2 RAT = 1200ps C = 21fF RAT = 2000ps C = 15fF ρ3 ρ4 RAT = 1800ps C = 18fF RAT = 2500ps C = 25fF Problem Formulation

8. CMP-aware RC Parasitics • Optimal (min-Cx) dummy fill pattern insertion • Pre-compute dummy fill pattern by enumeration [He-SPIE] • Tabulate both cap and fill pattern, indexed by wire width/space and fill amount • Post-dummy fill dishing/erosion calculation • Using Tugbawa-Boning’s model from MIT [Tugbawa-thesis] • Input: effective metal density, wire width/space

9. SBWF Algorithm • Extended dynamic programming [van Ginneken-ISCS] • CMP model is deterministic • Amount of variation calculated from metal features • Use CMP-aware RC • Prune sub-optimal/invalid partial solutions • Inferior: Cinf > Cn & ATint < ATn • Rise-time violation: Dsubtree > Dbound

10. Experiment • Experimental settings • ITRS 65nm (interconnect) & BSIM 4 (device) • RAT at sinks = 0, Tr < 100ps • SBW + Fill • Solving SBW using CMP-oblivious RC, i.e. no dishing/erosion/fill insertion • Risetime constraint set to 83ps during optimization to get solution that meets the Tr < 100ps constraint • Solution to be verified after under CMP-aware RC • SBWF • Simultaneous buffering, wire sizing and fill insertion

11. Experiment:SBW + Fill vs SBWF • r1 – r5: benchmarks from [Tsay-TCAD] • SBWF improves over SBW + Fill design • by 1.0% arrival time on average • by 5.7% power per switch

12. Outline • SBW and fill insertion (SBWF) under CMP variation • Modeling RC variation • CMP-aware SBW and fill insertion algorithm • Experiment: CMP-aware vs CMP-oblivious • Extension to Leff variation • Conclusion

13. T = Cumulative Probability 1 This portion subject to AT optimization Delay = Delay = Delay = RAT RAT @ 90% Statistical Buffer Insertion under Random Leff Variation • Leff variation leads to delay variation • Pick the solution with the desired distribution • Objective in this work: maximize “required arrival time” at the source for majority of dies

14. Modeling Buffer Delay due to Leff Variation • Buffer characterization by • Input capacitance (Cin) insensitive to Leff variation • For total Leff of a buffer at the largest 1% corner, input capacitance only increases by 3% • Output resistance (Reff) and intrinsic delay (Dbuf) sensitive to Leff and their variations are correlated • Joint probability density function: PDFR,d(Reff, Dbuf) • Delay with load Lbuf:Dload = Lbuf· Reff + Dbuf • Modeled by cumulative distribution functions (CDFs) • CDFd(L)(Dload) =

15. Challenges in Statistical Buffer Insertion Problem • Efficient manipulation of statistical calculation • Arrival time as a random variable for optimization • Captured by CDF • Calculation is slow by brute-force manipulation • Our approach: piece-wise linear (PWL) modeling • Pruning rules to remove sub-optimal options • Deterministic • AT1 > AT2 and L1 < L2 – establishes total order • Probabilistic • P(AT1 > AT2 Λ L1 < L2) – only forms partial order • eg. P(AT1 > AT2) = 0.6: sol 1 >> 2, but with a low probability

16. i j + i buf + i k min? j Statistical Operations in Buffer Insertion Problem • Buffer insertion-related timing calculation • Adding a wire • ATi = ATj – r*dij*Lj – 0.5*r*c*dij2 • Adding a buffer • ATbuf = ATi – d – Reff*Li • Merging two branches • ATi = min(ATj, ATk) • Key operations on variables • Statistical subtraction (addition) and minimum (maximum)

17. i j + i constant k + j buf + uncorrelated from independent subtrees Statistical Operations in Buffer Insertion Problem • Add: z = x + y (if x and y independent) • CDFz(t) = PDFx(t) ⊕ CDFy(t) • Max: z = max(x, y) (if x and y independent) • CDFz(t) = CDFx(t) * CDFy(t) • Independence of random variables • Adding wire • Adding buffer • Merging branches i

18. Modeling Cumulative Distribution Functions (CDFs) • CDF: PWL curve [Devgan-ICCAD] • Statistical addition (convolution) and maximum (multiplication) has closed-form solutions under PWL modeling • FAST!! • Sampling at pre-set percentile points on the y-axis is performed after operations to keep PWL form • PDF: Piecewise constant (PWC) curve • Obtained by differentiating the PWL of CDF

19. Key to Pruning: Definition of Dominance • CDF Dominance • Dominated curve completely on the L.H.S. of some others • Yield-cutoff dominance • Compare the AT only at the target timing yield rate (Yt) CDF Dominance Yield-cutoff dominance

20. still dominated dominated = ⊕ or * Not dominating one another under CDF Dominance, i.e., must keep both curves CDF Pruning • Accurate as it does not drop options that may lead to the optimal solution • Ineffective as it does not form total-order

21. log(runtime) (s) CDF Pruning Yield-cutoff Pruning wire length (um) Yield-cutoff Pruning • No partial-ordering issue, i.e. effective • Experimentally proven to achieve same accuracy as CDF Pruning

22. Experimental Settings • Experimental settings • Target timing yield rate at 90% • i.e. maximize the AT of 90% of dies • Risetime at any node has 99% chance < 100ps • SBW+Fill as our baseline • CMP as after-thought and no Leff variation • Requires over-constrained slew rate ratio 0.75 • i.e. design under 75ps to satisfy risetime constraint • vSBWF: SBWF + Leff variation

23. Definition of Timing Yield • AT with 90% timing yield for vSBWF • Yield rate at the same AT of SBW+Fill is only 25.1%

24. Experiment: SBW+Fill vs vSBWF • Timing yield • SBW+Fill: 45.7% on average • vSBWF: 90% as targeted • Runtime of vSBWF 8.3x that of SBW+Fill

25. Conclusion • Developed SBWF: CMP-aware buffering, wire sizing and fill insertion • Reduced 1.0% delay and 5.7% power • Extended SBWF to Leff random variation • Proposed efficient yet effective yield-cutoff pruning rules • Improved timing yield rate by 44.3% • Finished largest example (3000+ sinks) in 2 hours