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Balsa – Live @Eilat.fun

Balsa – Live @Eilat.fun. A Hands-on Tutorial Session Doug Edwards & A. Bardsley. Overview of Session. Balsa for Dummies Toolkit Language Features mini examples with hand-holding DIY Example Stack-based Calculator compile balsa & simulate locally generate xilinx bit stream in Manchester

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Balsa – Live @Eilat.fun

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  1. Balsa – Live @Eilat.fun A Hands-on Tutorial Session Doug Edwards & A. Bardsley

  2. Overview of Session • Balsa for Dummies • Toolkit • Language Features • mini examples with hand-holding • DIY Example • Stack-based Calculator • compile balsa & simulate locally • generate xilinx bit stream in Manchester • run on xilinx prototyping board

  3. Staff involved in Demonstration • Doug Edwards • presenter • John Bainbridge • demonstrator • Andrew Bardsley • principal author • (in Manchester !!)

  4. What is Balsa? • Language for synthesising large async circuits & systems • CSP/OCCAM background • Tangram-like • based on Tangram compilation function • compiles to a small (but expanding) set of handshake circuits • origins: ESPRIT 6143 EXACT project

  5. Handshake circuits – 1 • Circuits communicate along channels • Channels connect ports at circuit interfaces • Ports have: • Type • Direction • Sense

  6. Handshake Circuits – 2 • Port type determines the number of data wires • no data wires == control only port! • Port direction is input, output or control only • Port sense • Active: initiate transfers • Passive: respond to requests

  7. Pull Circuits – active inputs Pull Circuits: active ported circuits/ control driven req req data data cct ack ack active input port

  8. Pull Circuits Pull Circuits: Circuit demands data req req data data cct ack ack

  9. Pull Circuits Pull Circuits: data is supplied req req data data cct ack ack

  10. Pull Circuits Pull Circuits: validity is signalled req req data data cct ack ack

  11. Pull Circuits Pull Circuits: data is accepted and can then be released req req data data cct ack ack

  12. Pull Circuits Pull Circuits: circuit outputs data req req data data cct ack ack

  13. Pull Circuits Pull Circuits: circuit signals validity of data req req data data cct ack ack

  14. Pull Circuits Pull Circuits: data is accepted req req data data cct ack ack

  15. Pull Circuits Pull Circuits: data is released req req data data cct ack ack

  16. Pull Circuits Pull Circuits: ack is de-asserted req req data data cct ack ack

  17. Tool Overview balsa-mgr – GUI project manager balsa-md – makefile generator compilation toolssimulation tools tech mapping tools utility tools

  18. Design Flow

  19. Compilation Tools • balsa-c • compiles balsa programs to breeze • includes other breeze definition files • breeze is a handshake -circuit netlist format • acts as a library format for within Balsa • balsa-netlist • produces an EDIF netlist from a compiled balsa program • technology independent

  20. Simulation Tools • breeze2lard • produces a lard simulation file • various lard utilities • mainly hidden within the Makefile by balsa-md

  21. Tech Mapping Tools – 1 • Silicon back-ends • Compass • used in Amulet3 DMA controller • AMS 0.35 µ library within Cadence • in progress, but … • SGS 0.18µ • now available

  22. Tech Mapping Tools – 2 • Programmable Gate-Array back-ends • balsa-pv • generates powerview schematics & symbols • uses Viewlogic tools • balsa-xi • compiles design + test harness to xilinx parts • requires Xilinx tools

  23. Xilinx Families Supported • xilinx 4000e (used here) • runs on in-house prototyping boards • not optimised, will not be supported • xilinx virtex devices • future target for development • targeted at commercially available boards • XSV boards from Xess corp • 50K-800K gates @ $700-$1600 • 2Mbyte on board ram + peripherals

  24. Utilitity Tools • breeze2ps • creates a ps handshake circuit graph • breeze-cost • enumerates the handshake circuit used and gives an approximate area cost • balsa-md • automatic Makefile maker • balsa-mgr

  25. Balsa Language Features • Data types based on sequence of bits • Arrays and records are bit-based • Element extraction is by array slicing • Strict data typing • Structural iteration • Arrayed channels • Parameterised & recursive functions

  26. Balsa Language Features • Enclosed selection semantics • Allows passive ported circuits • Allows push (micropipeline-style) circuits • Allows un-buffered (latch-free) circuits

  27. Exercise 1a: Hello World Objective: understanding & compiling the simplest balsa program • go to directory ~/Balsa/Buffers • open file buffer1a.balsa (using your favourite editor)

  28. Example: Single Place Buffer import [balsa.types.basic] public type word is 16 bits procedure buffer (input i : word; output o : word) is local variable x : word begin loop i -> x; -- Input communication o <- x -- Output communication end end library mechanism visibility type declaration channel declarations procedure definition implies latch repeat forever sequential operation

  29. Exercise 1b: Hello World • compile the program: balsa-c buffer1a • list the files created • (examine the files if really curious)

  30. Exercise 2a: 2-place buffer Objective: illustration of parallel composition & modular compilation. • specify a 2-place buffer by composing two 1-place buffers • open file buffer2c.balsa

  31. i o c internal channel connects two 1-place buffers internal channel connects two 1-place buffers Code for 2-place buffer import [balsa.types.basic] import [buffer1a] public -- NB type word is declared previously procedure buffer2c (input i : word; output o : word) is local channel c : word begin buffer (?, ?) || buffer (?, ?) end reuse component parallel composition buffers connected by common signal names

  32. Exercise 2a: 2-place buffer • edit the buffer2c.balsa to replace the ‘?’s by appropriate channel names. • compile the program: balsa-c buffer2c • create a postscript plot of the handshake circuit graph & view it breeze2ps buffer2c gv buffer2c

  33. i o c Code for 2-place buffer import [balsa.types.basic] import [buffer1a] public -- type word has been declared in buffer1a procedure buffer2c (input i : word; output o : word) is local channel c : word begin buffer (i, c) || buffer (c, o) end buffers connected by by common channel name

  34. Exercise 2a: H/S Circuit Graph Top Level View

  35. Exercise 2b: A Flattened Circuit • Recompile the circuit & examine the handshake circuit produced: balsa-c -f buffer2c breeze2ps buffer2c gv buffer2c.ps

  36. Flattened View

  37. Exercise 3a: A modulo-16 Counter Objective: balsa type enforcement & simple use of balsa-md • go to directory ~/Balsa/Counters • open file count16a.balsa

  38. Code for modulo-16 counter procedure count16 (sync aclk; output count : nibble) is local variable count_reg : nibble begin loop sync aclk ; count <- count_reg ; count_reg := ( count_reg + 1 as nibble) end end handshake only input internal register await h/s on input then output count from internal register inc internal register assign result back to internal variable cast result back to correct size

  39. generate a test harness procedure name Exercise 3b: Simulation Objective: Simple Simulation • Generate a Makefile with test-harness rules balsa-md -t count16 count16a • Examine the Makefile • Run the simulation make sim | more (terminate with Ctrl-C)

  40. Exercise 3c: Simulation Results

  41. Exercise 3d: Graphical Simulation • Objective: using the LARD channel viewer • type make sim-win • run the simulation

  42. Running the Simulation • Stopping the simulation • Starting the simulation

  43. Lard Time View request (red) Channel values ack (green) cursor sensitive messages

  44. Passive Inputs • By default, Balsa generates circuit fragments with active ports • The select statement generates circuit fragments with passive inputs • select is normally a choice operator, but can be used with just a single input • What is a passive port?

  45. Exercise 4a: A Passive Input Counter Objective: Generate a counter with a passive input port • Open the file count16c.balsa

  46. Code for Count16c procedure count16 (sync aclk; output count : nibble) is local variable count_reg : nibble begin loop select aclk then count <- count_reg ; count_reg := ( count_reg + 1 as nibble) end end end but also select makes aclk a passive i/p select usually offers a choice

  47. Exercise 4b: Simulating the Counter • Remove the previous compilation make clean • Generate a new Makefile with a test-harness & run the simulation balsa-md -t count16 count16c make sim-win

  48. enclosing handhake

  49. Exercise 5a: A modulo-10 Counter • Open the file count10a.balsa

  50. Code for modulo-10 counter procedure count10(sync aclk; output count: C_size) is local variable count_reg : C_size variable tmp : C_size begin loop select aclk then if count_reg /= max_count then tmp := (count_reg + 1 as C_size) else tmp := 0 end ; count <- count_reg ; count_reg := tmp end -- complete select H/S end -- loop end end C_size and max_count previously declared if  then  else construct

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