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HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems

HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems. HW/SW Partitioning and Scheduling Algorithms. Presentation Outline. Introduction Basics/Preliminaries Problem Formulation Representative Approaches Conclusion. Introduction. Embedded Systems?

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HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems

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  1. HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems HW/SW Partitioning and Scheduling Algorithms

  2. Presentation Outline • Introduction • Basics/Preliminaries • Problem Formulation • Representative Approaches • Conclusion

  3. Introduction • Embedded Systems? • Special purpose/dedicated systems • Design Goals? • Highly optimized but Cost Efficient • Examples • embedded system provides a friendly interface • hand-held devices, such as a cellular phone or PDA • an industrial controller • safety-critical controller, such as an antilock brake controller in a car or an autopilot

  4. ASIC General Purpose Processor Dedicated Data path Digital Signal Processor Memory Generic Architectural Template

  5. HW/SW Co-Design • Need? • Increasing design complexities • Need to explore the design efficiently • CAD/Design Automation • Co-Design Steps • Co-specification: Specifications describing both HW/SW elements (and the relationship between them) • Co-synthesis: Automatic or semi-automatic design of HW/SW to meet a specification • Co-Simulation: Simultaneous simulation of HW/SW elements, often at different levels of abstraction

  6. Co-Synthesis Problem • Partitioning the functional description between HW and SW • Allocating processes to processing elements (PEs) • Scheduling processes on the PEs • Binding processing elements to particular component types

  7. Embedded CPU On Chip SRAM/ Cache Dynamically Reconfigurable Data path Dynamically Reconfigurable Logic • Alternative to conventional ASICs and general-purpose processors • post-fabrication customized for a wide class of applications • partially reconfigured at run-time to implement different tasks without effecting computation of other tasks

  8. Inputs Specification • Task Graphs • Estimation/Profiling • Resource Libraries

  9. DRL Architecture Model • Frame: atomic reconfiguration storage unit that can be dynamically updated • Multiple frames reconfigured one by one • Reconfiguration of one frame does not disturb the execution of other frames

  10. Partitioning and Scheduling • Partitioning • Coarse Grained – Tasks Level • Fine Grained – Basic block Level • Scheduling • Static (design time) • Dynamic (At run time)

  11. Challenges of Using DRL • Reconfiguration management • Goal: To minimize no. of reconfigurations • Reconfiguration Delays Execution • Reconfiguration Consumes Power • How? • Tasks Ordering • Pre-fetching

  12. Representative Co-synthesis Systems • CORDS – Princeton University • CRUSADE – Bell Labs • SLOPES – Princeton University • NIMBLE Compiler • Recent – Run-time Scheduling (by Juanjo Noguera, Rosa M. Badia)

  13. NIMBLE Compiler • partitioning algorithm • selects which loops to implement in the FPGA, and which hardware version of each loop should be used to achieve the highest application-level performance

  14. NIMBLE Compiler • Multiple Loop Implementations in HW

  15. NIMBLE Compiler • Heuristic Using Loop Procedure Hierarchy Graph

  16. SLOPES • Multi-objective: Price Power Performance • Genetic Algorithm for Partitioning and Allocation • Scheduling Heuristic • takes into account the delay and power overheads of dynamic reconfiguration

  17. Scheduling Issues • Scheduling sequence • multiple ready tasks may reside candidate pool • different time, resource and reconfiguration requirements, and power consumption • changing the scheduling order may have a significant impact on scheduling quality

  18. Scheduling Issues • Location assignment policy • possible positions in the FPGA where the circuit implementing the task can be located • different locations not only influences the current task, but may also impact the tasks scheduled either after or before it

  19. SLOPES Scheduling • Scheduling sequence • The order of scheduling tasks is determined dynamically by task priorities • Location assignment policy • The global reconfiguration information for all the tasks assigned to the FPGA is considered

  20. Examples

  21. Scheduling Sequence Policy • Dynamic Priority Assignment

  22. Location Assignment Policy • Reconfiguration prefetch • Configuration pattern reutilization • Eviction candidate • Fitting policy • Slack time utilization

  23. Location Assignment Policy • Frame Priorities

  24. Dynamic Run-time Scheduling • Motivations • Data Dependent Computation • Multi-functions Systems

  25. Proposed Architecture Model

  26. Partitioning: List Based

  27. Scheduler

  28. Scheduling

  29. Conclusion • Low delay reconfigurable devices • Automated Co-synthesis • Systems using DRL are able to meet specifications Cost Efficiently • Reduced Design Time

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