Instructor: Dr. Phillip Jones (phjones@iastate) Reconfigurable Computing Laboratory

1. ECpE 583Reconfigurable ComputingLecture 21: Thur 11/06/2008(Placing Applications onto FPGAs: Part II) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://www.ece.iastate.edu http://class.ece.iastate.edu/cpre583 (coming soon) http://www.arl.wustl.edu/~phjones/cpre583 (temporary)

2. Class Announcements • Updated schedule (coming soon) • MP2 concerns

3. Outline • Placing an application on an FPGA • Low-level details

4. Applications on FPGA • Low-level: Application to FPGA refs • Reconfigurable Computing (2008) • Scott Hauck, Andre DeHon • The VLSI handbook (2000) • Wai-Kai Chen (note: there’s a 2nd edition (2006)) • Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays • Jason Cong (TODAES’96)

5. Applications on FPGA: Low-level • Implement circuit in VHDL (Verilog) • Simulate compiled VHDL • Synthesis VHDL into a device independent format • Map device independent format to device specific resources • Check that device has enough resources for the design • Place resources onto physical device locations • Route (connect) resources together • Completely routed • Circuit meets specified performance • Download configuration file (bit-steam) to the FPGA

6. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

7. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

8. Implement Design • Several methods of design entry • HDL: VHDL, Verilog • Higher level languages: HandleC • Schematic Capture

9. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

10. Design Simulation • Compile Implemented design (e.g. in VHDL) into a format understood by a simulator • vcom: ModelSim’s compiler • Simulate Design • vsim: ModelSim’s simulator

11. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

12. (Logic) Synthesis • Technology independent representation • EDIF (Electronic Design Interchange Format) • Technology independent optimization • Combinational optimization • 2-level • Multi-level • Sequential optimization • FSM state reduction • retiming

13. EDIF representation • Gives a standard means to target a design to different vendors

14. Combinational Optimization • 2-level example

15. Combinational Optimization • multi-level example (Berkley MIS)

16. Sequential Optimization • State reduction example

17. Sequential Optimization • Retiming example

18. (Technology) Map • Translate device independent net list to device specific resources • Rule based • Tree based

19. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

20. (Technology) Map • Rule based example

21. (Technology) Map • Tree based example

22. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

23. Place • Bind each mapped resources to a physical device location • General Purpose • Clustering • Simulated Annealing • Partition-based • Structured Guided • Data Path based • User Guided Layout

24. Place (General Purpose) • Places resources without any knowledge of high level structure • Guided primarily by local connections between resources

25. Place (General Purpose) • Placement using clustering

26. Place (General Purpose) • Placement using simulated annealing

27. Place (General Purpose) • Placement using partitioning

28. Place (Structured-based) • Automatically leverage structure of the application • Algorithms my work well for a give structure, but will likely give unacceptable results for an design with little regular structure.

29. Place (Structure-based) • Datapath-based example

30. Place (User-Guided) • User provide information about applications structure to help guide placement • Can help remove critical paths • Can greatly reduce amount of time for routing • Several ways to provide guide information • VHDL directives (e.g. RLOC) • GUI-based (e.g. Xilinx FloorPlanner)

31. Place (User-Guided) • User-guided placement example

32. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

33. Route • Connect placed resources together • Two requirements • Design must be completely routed • Routed design meets timing requirements • Widely used algorithm “PathFinder” • PathFinder (FPGA’95) • McMurchie and Ebeling • Reconfigurable Computing (Chapter 17) • Scott Hauch, Andre Dehon (2008)

34. Route (PathFinder) • PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs (FPGA’95)

35. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

36. Download • Convert routed design into a device configuration file (e.g. bitfile for Xilinx devices)

37. Next Lecture • Compute Models: Part I • Recommended Reading • Design Patterns for Reconfigurable Computing • http://ic.ese.upenn.edu/abstracts/despat_fccm2004.html

38. Questions/Comments/Concerns • Write down • Main point of lecture • One thing that’s still not quite clear • If everything is clear, then give an example of how to apply something from lecture OR