IN2305-II Embedded Programming

1. IN2305-IIEmbedded Programming Lecture 2: Digital Logic

2. Main Subjects • Combinational logic: no memory (state) • Sequential logic: state (clocked) • VHDL implementation issues • How to model / synthesize digital circuits

3. VHDL in a Nutshell behavioral versus structural specification: structural = composition (“wiring”) concurrent execution model: everything executes in parallel (data flow) y <= x or c; c <= a and b; z <= y when p else not y when not p; process (s) begin a <= not s; end process; -- a <= not s; sequential behavior (state): z <= y when p; -- no else => latch process (clk) begin y <= x; -- sample x when clk changes -> latch if clk = ‘1’ then q <= d; -- d-ff (pos edge-trig) end process; note: within process: sequential execution model

4. a y b a y a y b Combinational Logic y <= a and b; y <= a or b; y <= not a; Essence of combinatorics: process triggered by the input events (y assignment is synchronous with a and b signal changes)

5. Example Combinational Blocks 2 with a select -- dec z <= “0001” when “00”, “0010” when “01”, “0100” when “10”, “1000” when “11”; y <= z when d = ‘1’ else “0000”; a dec 4 y d with a select -- enc y <= “00” when “0001”, “01” when “0010”, “10” when “0100”, “11” when “1000”; 4 enc 2 a y

6. 8 8 8 Example Combinational Blocks with s select -- mux y <= a when ‘0’, b when ‘1’; a y mux b s a with op select -- alu y <= a + b when ‘00’, a and b when ‘01’, ... y b op

7. Sequential Logic process (clk) -- d-ff begin if rising_edge(clk) then q <= d; end if; end process; d dff q clk Essence of state: assignment is NOT triggered by input events but by an auxiliary signal (usually called a clock) process (d) -- buffer begin q <= d; -- only sensitive to d => combinational! end process;

8. Comb. + Sequential: FSM process -- fsm begin wait until rising_edge(clk); case s is when 0x”00” => if (x = ‘1’) then s <= 0x”01”; end if; y <= ‘1’; when 0x”01” => .. .. end case; end process; x y cmb s dff clk Mealy FSM: y = f(s,x) Moore FSM: y = f(s)

9. Example Sequential Blocks (1) d process -- ram begin wait until rising_edge(clk); if (we = ‘1’) then mem(a) <= d; end if; y <= mem(a); end process; a y ram we clk

10. Example Sequential Blocks (2) process -- counter begin wait until rising_edge(clk); if (rst = ‘1’) then c <= (others => ‘0’); else c <= c + 1; end if; y <= c; end process; y rst ctr clk

11. Tri-state Logic: Busses y y <= a when oe_a = ‘1’ else ‘Z’; a oe_a y <= b when oe_b = ‘1’ else ‘Z’; b dec oe_b More efficient than mux for n-bit data paths

12. Simple Processor (Delta) rom dec .. pc data bus r0 r1 ... rn alu a

13. VHDL Implementation Issues • Structural synthesis • entities reg, tristate-buf, rom, enc, alu, connected by bus • each entity behavioral • example: Delta-1 source code • Behavioral synthesis • entities cpu, rom • cpu entirely behavioral • example: X32 source code • pro: simple, understandable code, virtually no HW design • con: more burden on synthesizer, less efficient HW (space), potentially larger critical path which may lead to slower freq. • Trade-off depends on appl. and available resources

14. Behavioral Approach process -- delta cpu (behavioral) begin wait until rising_edge(clk); .. case op is when .. => pc <= op(..); -- jp .. when .. => r(a) <= acc; -- st r.. when .. => acc <= acc + op(..); -- add #.. when .. => acc <= acc and r(a); -- and r.. when .. => if (zero = ‘1’) then -- bz .. pc <= op(..); end if; end case; if (-- not jp/bz/bc/..) then pc <= pc + 1; end process;

15. e tmr t clk Button Debouncer x x: Vcc y: time GND x’ x t’ x t,x 0 1 2 0: output’, timer enable’ 1: output, timer enable 2: output, timer enable’ t,x’ x’

16. Debouncer Code (1) process -- fsm (behavioral) begin wait until rising_edge(clk); case s is when “00” => if (x = ‘1’) then s <= ”01”; end if; when ”01” => if (t = ‘1’) then s <= “00” when (x = ‘0’) else “10” when (x = ‘1’); end if; when “10” => if (x = ‘0’) then s <= “00”; end if; end case; output <= ‘0’ when (s = “00”) else ‘1’; timer_enable <= ‘1’ when (s = “01”) else ‘0’; end process;

17. Debouncer Code (2) process -- timer (behavioral) begin wait until rising_edge(clk); if (timer_enable = ‘0’) then counter <= (others => ‘0’); t <= ‘0’; else if (counter < THRESHOLD) then counter <= counter + 1; else t <= ‘1’; end if; end if; end process;

18. Demo using FPGA board • FPGAs are a flexible, low-cost “bread-board” to experiment with HW using SW (VHDL) instead of ICs and wires • Xilinx Board: • Cheap: $99

19. Demo Demo .. (vhdl_projects.tgz, debouncer)

20. Autorepeat input: output: time t1 t2 t2 i’ t1’.i t2’.i t2’.i i t1.i t2.i /o’ /o /o’ /o i’ t2.i i’ t2 i’ clk

21. Autorepeat Code process -- fsm, using counter is more simple begin wait until rising_edge(clk); case s is when “00” => if i = ‘1’ then c <= ..; s <= ”01”; end if; when ”01” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c > .. then c <= ..; s <= “10”; end if; when “10” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c > .. then c <= ..; s <= “11”; end if; when “11” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c > .. then c <= ..; s <= “10”; end if; end case; output <= ‘1’ when s = “01” and s = “11” else ‘0’; end process;

22. Demo Demo .. (vhdl_projects.tgz, reaction timer)