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Lecture 04 CMOS Family Ties No More Static

Lecture 04 CMOS Family Ties No More Static. ENGR 3430 – Digital VLSI Mark L. Chang Spring ’06. pMOS Problems. Static CMOS is great Most logic you design is static CMOS Pull-up block can get pretty big: 6-input NOR. Pseudo-nMOS. Static logic requires 2n transistors for n-input gate

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Lecture 04 CMOS Family Ties No More Static

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  1. Lecture 04CMOS Family TiesNo More Static ENGR 3430 – Digital VLSI Mark L. Chang Spring ’06

  2. pMOS Problems • Static CMOS is great • Most logic you design is static CMOS • Pull-up block can get pretty big: 6-input NOR

  3. Pseudo-nMOS • Static logic requires 2n transistors for n-input gate • Pseudo-nMOS: n+1 transistors for n-input gate • Pull-up pMOS sized about ¼ strength of pull-down network • Eliminates long chain in pull-up network • Static power dissipation

  4. More Pseudo-nMOS Gates • NAND • NOR • Generic

  5. Weak Transistors

  6. Pseudo-nMOS Power • Pseudo-nMOS draws power whenever Y = 0 • Called static power P = I•VDD • A few mA / gate * 1M gates would be a problem • This is why nMOS went extinct! • Use pseudo-nMOS sparingly for wide NORs • Turn off pMOS when not in use

  7. Cascode Voltage Switch Logic • Try and eliminate static power dissipation • Still reduced number of pMOS transistors

  8. Dynamic Logic • Dynamic gates uses a clocked pMOS pullup • Two modes: precharge and evaluate

  9. The Foot • What happens when pulldown is ON during precharge?

  10. Logical Effort of Dynamic Circuits

  11. Nothing for free, though • Can we make all transitions? • 0 -> 0 • 0 -> 1 • 1 -> 1 • 1 -> 0

  12. Monotonicity • Dynamic gates require monotonically rising inputs during evaluation phase • 0 -> 0 • 0 -> 1 • 1 -> 1 • 1 -> 0

  13. Cascading Dynamic Logic • Dynamic gates produce monotonically falling outputs during evaluation • Therefore, illegal to cascade them in series

  14. Hmmm… • Can we solve the montonicity problem?

  15. Domino Logic • Follow dynamic logic with static inverter • Dynamic/static pair called domino gate • Produces monotonic output

  16. Domino Logic • Follow dynamic logic with static inverter • Dynamic/static pair called domino gate • Produces monotonic output

  17. precharge precharge precharge pull-down network pull-down network pull-down network Domino Logic • Each domino gate triggers next one, like a string of dominos toppling over • Gates evaluate sequentially but precharge in parallel • Thus evaluation is more critical than precharge • HI-skewed static stages can perform logic

  18. Domino Example • 8-input MUX

  19. precharge pull-up network precharge pull-down network pull-down network precharge Zipper Logic • Alternate blocks of n and p-type logic • Similar to domino but transistors are easier to pack since there are equal numbers of each type on average • pMOS can get big, though

  20. Leakage • Dynamic node floats high during evaluation • Transistors are leaky (IOFF 0) • Dynamic value will leak away over time • Formerly miliseconds, now nanoseconds! • Use keeper to hold dynamic node • Must be weak enough not to fight evaluation

  21. Charge Sharing

  22. Hmmm… • Can we solve the charge sharing problem?

  23. Secondary Precharging • Solution: add secondary precharge transistors • Typically need to precharge every other node • Big load capacitance CY helps as well

  24. Noise Sensitivity • Dynamic gates are very sensitive to noise • Inputs: VIH Vtn • (logical “high” is anything over threshold) • Outputs: floating output susceptible to noise • Noise sources • Capacitive crosstalk • Charge sharing • Power supply noise • Feedthrough noise • And more!

  25. Domino Logic Summary • Domino logic is attractive for high-speed circuits • 1.5 – 2x faster than static CMOS • But many challenges: • Monotonicity • Leakage • Charge sharing • Noise • Widely used in high-performance microprocessors

  26. Pass Transistor Logic • Use pass transistors like switches to do logic • Inputs drive diffusion terminals as well as gates • CMOS + Transmission Gates: • 2-input multiplexer • Gates should be restoring

  27. LEAP • LEAn integration with Pass transistors • Get rid of pMOS transistors • Use weak pMOS feedback to pull fully high • Ratio constraint

  28. CPL • Complementary Pass-transistor Logic • Dual-rail form of pass transistor logic • Avoids need for ratioed feedback • Optional cross-coupling for rail-to-rail swing

  29. Summary • There are lots of CMOS logic families • See Table 6.4 in your book • Static CMOS is 95% of your circuit • Dynamic logic is difficult to implement, but can be significantly faster • Sensitive to noise • May depend on ratios (process variation can be troublesome) • Leakage, charge sharing • Requires careful timing

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