Modeling TSV Open Defects in 3D-Stacked DRAM

1. Modeling TSV Open Defects in 3D-Stacked DRAM Li Jiang†, Liu Yuxi†, Lian Duan‡, Yuan Xie ‡, and Qiang Xu† Presenter: Qiang Xu †CUhkREliable Computing Laboratory Department of Computer Science & Engineering The Chinese University of Hong Kong ‡Department of Computer Science & Engineering Pennsylvania State University, USA

2. Purpose • New test challenges for 3D-stacked DRAM • Massive amount of TSVs that are prone to open defects and coupling noises • Conduct extensive simulation to study the faulty behavior of TSV open defects

3. Outline • Introduction • Motivation • Simulation Methodology • Simulation Results • Conclusion

4. Why 3D-Stacked DRAM? • Ever-increasing performance gap between processor and memory • Excessive latency • Limited bandwidth • 3D-stacking is a promising solution to tackle this “Memory Wall” problem

5. DRAM TSV 4 Gbit density RD/WR I/O Buffer TSV PCB Interposer 8 strata Peripherals 3 Gbps/pin NEC: 4Gb, 8 Layers 3D-Stacked DRAM is Already Here … SamSung: 8Gb, 4 Layers

6. “True” 3D-Stacked DRAM • Much better performance when compared to using TSVs only for buses • TSV density is extremely high One rank in multiple layers Separate peripheral logic layer Loh ISCA’08

7. Motivation • TSVs are prone to open defects • Contamination • O2 trapped in bonding surface • Miss Alignment/dislocation • Mechanical failures in TSVs • Contact resistances Voids during filling M. Kawano, et al. IEDM’06

8. Motivation I. Savidis et.al. ISCAS08 Capacitive coupling between adjacent TSVs is NOT negligible!

9. Write Operation Read Operation 3D Memory Model 0 0 0 0 Enable 1 1 1 1 1 0

10. Simulation Setup • SPICE simulation • Open defect represented by a very large resistance • Vdd 1.8v, Vth 0.6v • Coupling capacitance is set according to previous work

11. Simulation Schematic for Wordline Open WL2 Ropen WL0 WL1 Vsig X

12. Wordline Open • Access the open wordline • Access the neighboring wordline of open wordline • Vary wordline load capacitance • Vary trapped charges in pass-transistor

13. 0 1 Wordline Write • No Access to open wordline • Access its neighboring wordline of the (WL1) • Write 1 to Cell4 • Write 0 to Cell4 • Strong write 0 (1w0),Weak write 1 (0w1) 0 1 0 1

14. 1 0 Wordline Read C4 1 0 0 • Multiple Access • Two scenarios: • Cell in the same bitline • Cell in Complemented bitline C7 0 0 1 0 (Cload=200fF) (Vtrap>0.7V) (Vtrap>1V)

15. Simulation Schematic for bitline Open Ropen SE Aggressor Victim Aggressor

16. Bitline Read 0 1 0 0 • Access WL0,No Error • C1 BLiBLi • Access WL1, • C6BLi+1BLi • C4BLi-1BLi-1 BLi • Driving force determine the output of open bitline Vref

17. Coupling from Multiple Layer • More complicated coupling effect • Interference from other layer

18. Fault Modeling • No Access • Multiple Access • Coupling by neighbor

19. Conclusion • The massive amount of TSVs used in “True” 3D-stacked DRAM are prone to open defects and coupling noises • We model the faulty behavior of open TSVs and show their effects through extensive simulation

20. Thank you for your attention !