1 / 18

PowerPC 601

PowerPC 601. Stephen Tam. To be tackled today. Architecture Execution Units Fixed-Point (Integer) Unit Floating-Point Unit Branch Processing Unit Cache Unit Memory Management Unit (MMU) Pipeline Structure Instruction buffer Multiply-Add Benchmark. PowerPC Processors.

duscha
Download Presentation

PowerPC 601

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. PowerPC 601 Stephen Tam

  2. To be tackled today • Architecture • Execution Units • Fixed-Point (Integer) Unit • Floating-Point Unit • Branch Processing Unit • Cache Unit • Memory Management Unit (MMU) • Pipeline Structure • Instruction buffer • Multiply-Add • Benchmark

  3. PowerPC Processors • The PowerPC 6XX line of microprocessors from IBM, Motorola and Apple • viewed that personal PC’s would be required to fulfill and accommodate more power and resource intensive applications such as those associated with multimedia. • Four implementations of the PowerPC architecture were initially announced: • PowerPC 601 - Original PowerPC microprocessor • PowerPC 603 - Low-cost, least powerful and consumes the least amount of power • PowerPC 604 - Faster, higher performance. • PowerPC 620 - The first 64-bit implementation of the PowerPC architecture. • The PowerPC 601 is a high performance super-scalar processor implementing 3 independent execution units and 2 register files • Execution (pipeline processing) units: • Integer Unit (IU) or Fixed-Point Unit (FXU) • Floating Point Unit (FPU) • Branch Processing Unit (BPU)

  4. PowerPC 601 Basic architecture Load/store Instruction length 32 bit Byte/halfword load and store Yes Condition codes Yes Conditional moves No # of Integer registers 32 Integer register size 32/64 bit # of Floating point registers 32 Floating point register size 64 bit Floating point format IEEE 32 bit, 64 bit Virtual address 52-80 bit 32/64 bit mode bit Yes Segmentation Yes Page Size 4 Kbytes Instruction/data cache size 32 Kbytes Clock speed 50-100 MHz Features

  5. PowerPC 601 Architecture • there are wide buses for memory, internal processor transfers, registers and on-board processing units.

  6. Fixed-Point (Integer) Unit & Floating-Point Unit • FXU(IU) • Executes one instruction at a time • Most instructions are single cycle instructions • Interfaces with cache and MMU • FPU • Contains: • Single precision multiply-add array • Floating-point status and control register • 32 64-bit registers • Buffers 2 extra instructions when FPU is busy • Supports IEEE 754 FP data types

  7. Branch Processing Unit • Contains: • An adder to compute the target address • 3 special purpose registers • Link register (LR) • Count Register (CTR) • Condition Register (CR) • Performs look ahead in condition branches into CR • Uses dedicated registers other than the General Purpose Registers (GPR)

  8. Branching &Branch Prediction • The 601 has special purpose registers in the BPU for holding, operating on and testing conditions • A single branch instruction may implement a loop-closing branch by decrementing the hardware counter CTR, testing its value and branching if non-zero • For unconditional branches or ones that only depend on the CTR, the branch is executed immediately and is considered a zero cycle branch. • Branch prediction is uses static branch prediction made by the compiler • To protect against wrong predictions • the contents of the instruction buffer are save for a short period of time until instructions from the take paths are delivered from memory • allows for instructions for the non-taken path to be available immediately if a wrong prediction is made.

  9. Cache Unit & Memory Management Unit • 32 Kbytes • 8-way associative • Unified (instruction and data) • Has 2 ports • Instruction fetch • “snooping” transactions on system interface • Supports (externally) 4 PetaBytes(252) of virtual memory and 4 Gb of physical memory • Implements demand paging for VM

  10. Pipeline Structure Fetch Up to eight instructions are fetched into an instruction buffer Dispatch Instructions are dispatched to either the FXU or FPU Decode Instructions are decoded, with the source registers being read Instructions to the FXU are decoded together in the dispatch stage. Execute This stage exists in the BPU as well as the FXU, where integer instructions execute and cache lookup and address processing also occur Execute1 FPU multiplication Execute2 FPU addition Cache Floating-point operands are sent to the FPU and the integer operands are sent to the FXU. Write Register file write.

  11. Instruction Buffer • The 601 has several buffers in the pipelines that allow storage of multiple fetched instructions and also the storage of several dispatched instructions. • allows out-of-order dispatching (therefore, when a pipeline is blocked, dispatching may still continue to non-blocked ones) • cache is unified meaning that both the instruction and data share a cache • data and instructions will need to contend for cache access • fetched instruction buffer of 8 instructions (even though the maximum processing rate is 3 instructions per cycle) • data will have priority, the instructions are fetched and stored while it is able to

  12. Hence… • Up to three 32-bit instructions may be dispatched each cycle • one each to FXU, FPU and BPU • The unified cache provides • A 32-bit interface to the FXU • A 64-bit interface to the FPU • a 256-bit interface to both the instruction and memory queues • The I/O had a 32-bit address bus and a 64-bit data bus • These buses are logically and physically decoupled from one another for support of piplined, non-pipelined, or even split bus transactions • To reduce latency and increase performance, the 601 itself is capable of pipelining up to two outstanding operations onto the bus

  13. Multiply-Add • PowerPC 601 takes in three operands • processes (A x B + C) or (A x B – C) in a single instruction • Assuming program and data are cached, a 100-MHz 601 can sustain 100 million MACs (multiply-accumulate operations) per second on some digital filters

  14. Benchmarking

  15. Direct Benchmark Comparison with ADSP-2106x

  16. More Benchmark Comparisons

  17. General Purpose Processor • Why use DSP when benchmarks show GPPs like PowerPCs perform better? • Performance gained from complicated dynamic features • Not suited for real-time applications • Decreased real-time predictability • Complicated optimizing code

  18. References • Hoskins, John, “The PowerPC Initiative”, 1995, http://www.eng.uci.edu/comp.arch/processors/powerpc/PCPower.html • Smith, James; Weis, Shlomo, “PowerPC 601 and Alpha 21064: A Tale of Two RISCs”, IEEE- Computer, June 1994, Vol. 27, No. 6, Page 46-58 • Lee, Ben, “Chapter 2: A Simple SuperScalar Processor – PowerPC 601”, http://www.ece.orst.edu/~benl/Courses/ECE570_w02.html • “PowerPC Microprocessor- White paper”, http://www1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power/ppc_601.html • Durisety, Chandra S.A., “PowerPC 601”, http://www.ece.msstate.edu/~cad12/PowerPC601.ppt • “Analysts Show CPU Can Handle Some Signal-Processing Tasks”, Microprocessor Report, May 8, 1995 • http://www.bdti.com/articles/info_articles.htm

More Related