1 / 60

NDFA Based Scheduling

NDFA Based Scheduling. Forrest Brewer, Steve Haynal University of California Santa Barbara. Scheduling is Behavioral Synthesis. Exploits fundamental freedom -- ordering and binding of operations, operands

dustin
Download Presentation

NDFA Based Scheduling

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. NDFA Based Scheduling Forrest Brewer, Steve Haynal University of California Santa Barbara Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  2. Scheduling is Behavioral Synthesis • Exploits fundamental freedom -- ordering and binding of operations, operands • Subdivided into DFG transformation, resource allocation, time-scheduling, operation binding, memory binding, communication binding, resource modeling, reallocation... • Complexity of tasks requires top-down flow -- yet evaluations/constraints are bottom-up • Behavioral Synthesis difficult to use! • Seemingly trivial changes cause vast output changes • Design tradeoffs tied to a particular point language (~VHDL, ~Verilog, Silage, Esterel...) • No direct control of implementation • No direct control of binding, mapping • No distinction between problem statement and constraints • No canonical representation of design space • Fundamental problem covers enormous scope • Universality issues in specification • How to capture design mapping knowledge? • How to create verifiable design representation without canonical model? • Our viewpoint -- wrong problem Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  3. Simpler Problem • Assume Designer creates the design • Support incremental refinement of design at all levels of representation • Support incremental design synthesis when possible • Provide well defined hierarchy on which to place constraints, trial implementations ... • Provide mechanism for subsystem abstraction, modeling and evaluation at each level • How to do this? • Drop representation distinction between logic, module, and sub-system levels • Drop potential for universality in internal representations • Create mechanism for automatic design abstraction within designer's design decomposition • Use efficient representation of fundamental model • Provide feedback to designer for evaluating both the design itself and the representation • Where do we start? • Interface Protocols are key complexity growth problem • Designer constructs system model with abstract protocols, required data-flows, possible maps • Generalize scheduling to provide possible sequencing of sub-systems into systems meeting external protocol constraints (models) Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  4. Protocol Constrained Scheduling • Problem: Conventional scheduling algorithms cannot accommodate the typical complex sequencing and timing constraints of modern design. • Three Problems: Specification, Scheduling, and Problem Scale • Specification: How to specify the required timing in an concise, explicit way? • Scheduling: How to systematically exploit mapping freedom while meeting the timing requirements? • Problem Scale: Problems of interest to industry are enormously complex! • Idea: Protocol specification is amenable to NDFA modeling -- so create automata-based model to represent Control/Data-flow freedom => All possible implementations exist as sequences of states of the joint automaton Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  5. Protocol Specification • Sequencing complexity of digital system interfaces increasing • Specification languages Verilog?, VHDL require implicit protocol specification • Alternative specification via NDFA automata (e.g. PBS, Esterel, Custom point language) • Representation is finite • Synthesis can be very efficient -- can handle very complex designs • Provides mechanism for time sequence specification relatively independent of data-flow control semantics • Protocol + CDFG semantics + mapping abstractions make a complete model • No ad-hoc mapping library (beyond control of designer) • No convenient dependency binding assumptions (to be worked around by designer) • No encrypting desired sequential FSM in higher level language! • Designer specifies event sequences he wants • System evaluates/synthesizes ensemble FSM Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  6. Design Representation • Model System as hierarchy of design frames • Frames have external protocol specification NDFA, CDFG, and allowed Mappings • Frames contain instances of other frames abstractions (abstracted NDFA/CDFG model) • Resource utilization and sharing restricted to within a design frame Sub-frame Model Control Data Flow Graph Frame External Protocol Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  7. Hierarchy of Refinement • Exact protocol scheduling intractable for practical large problems • Hierarchy of Refinement • partition the problem into manageable abstractions • hides lower level details • allows systematic high-level pruning of designs before more detailed treatment • Completed sub-frame designs can be abstracted to high level component models • allows incremental design change/refinement at any level • --provides mechanism for consistency verification Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  8. Protocol Scheduling Implementation • Represent CDFG model as Causal (NDFA) Automaton • Generalization of current scheduling model • Models all valid data flows • Models code hoisting, unrolling, transformations... • Represent External Protocol as NDFA automaton • Very general, efficient model • Synchronous timing model (can be generalized-- future work) • Alternative behavior as NDFA alternatives • CDFG maps I/O operations among sub-frames • Sub-frames have interface protocols, abstracted CDFG semantics • Construct ensemble automata model with all valid sequences of events meeting internal and external protocols and causal data-flow constraints • Need only find complete sub-set of all possible states for solution Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  9. Scheduling Solution • Every schedule is some subset of states of the ensemble automaton • Must construct causal and complete set of states • Exact solution strategies: • Construct all states up to resource bounds • Depth-first search of states • Heuristic search -- choose good path, complete schedule automatically • Prune solution space • Additional constraints or objectives -- technique works best when highly constrained • Heuristic strategies: • Sub-set BDD representation of reachable states • Incremental search (this is not verification!) • Possible objectives: • Communication • Temporary storage (memory) • Performance • Control complexity Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  10. Input 0 1 0 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 1 1 Output 0/0 0/1 a c 0/0 1/0 0/1 1/1 b d 1/0 1/1 DFA Model of Two Stage Pipe • Input = 1 indicates operands are supplied to the pipe • Output = 1 indicates operand is produced by the pipe State a b c b d c b d d c a Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  11. Input 0 1 0 1 1 0 1 1 1 0 0 Output 0 0 0 1 0 1 1 0 1 1 1 State a a,b a,c a,b a,b,c a,c a,b a,b,c a,b,c a,c a -/ -/ 1/ a b c -/1 NDFA Protocol for Two Stage Pipe • Inputs and outputs same as DFA model • Some transitions produce no outputs Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  12. A B C * * D E * Operand Scheduling a CDFG on NDFA Protocol • CDFG to Schedule: • Two stage NDFA protocol description for component • Protocol alone is insufficient -- need internal data-flow requirements • Mapping is trivial (in this case) • Protocol + CDFG is sufficient -- but also describes information not needed externally • Solution: Simplify scheduling solution of sub-frame to make abstracted model Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  13. A C -/ * * 1/ -/ B a b c D * E -/1 Input 0 1,A,B 1,D,E 1,t,C 0 0 0 1,A*B*C Output 0 0 0 1,t,C 1,D*E 0 State a a,b a,b,c a,b,c a,c a a Operand Schedule on NDFA Protocol • Optimal one multiplier schedule (co-execution of protocol and causal automata): Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  14. Causal Automaton Formulation of Scheduling • Scheduling Problem (V, E, C, R) • vertexv eV is an operation • edge(u,v) e E is a directed edge representing a data dependency • hyper-edge{vc,VTc,VFc} groups a control operation and corresponding subsets of operations • hyper-edge{bound, (T m V)}e R represents a resource bound applied to a subset of (mapped) operations • The edge set is partitioned into a forest of forward edges and a subset of looping edges which point backward • Scheduling solution is a complete, compatible set of deterministic sequences of vertices such that all dependencies are causal and all resource bounds are met at each state, and the set has sequences for each possible future value of the set of controls. • In the following, we will discuss minimum latency and maximal throughput as objective functions. Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  15. 0 1 j1 Single-Cycle Operation Modeling Automata • 00 Operation unscheduled and remains so 1 1 00 01 1 0 • 01 Operation scheduled next cycle • 11 Operation scheduled and remains so • 10 Operation scheduled but result lost Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  16. …. h i k 0 0 0 1 1 1 Scheduling Automata: • State represents current set of available operands and state of modeling protocol automata • Constraints on transitions • Representation Compact • Product of Mapped Modeling automata for each resource protocol Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  17. h i 11 01 01 j 11 00 11 00 01 11 00 01 01 01 01 00 01 01 01 Resource Bounds • 01 indicates resource • Resource bounds constrain simultaneous 01 transitions • Iterative constraint on CA • ROBDD representation: • 2 |bound| |operations| One Resource Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  18. j i h Dependency Implication • All transitions in which j is active before all of its predecessors are known are removed • BDD Complexity is O(|predecessors| * |operations|) Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  19. i j h i0h 000 i00 ij0 00h i0h ijh ij0 i00 ij0 i0h ijh ijh 000 i00 ij0 00h i0h ijh 000 00h 000 i0h 00h ij0 i00 ijh 000 i00 ij0 00h i0h ijh 000 00h ij0 i00 ijh i00 00h ijh i0h 000 ij0 i00 000 i0h 00h Example NFA • Assume 1 resource • Transition relation induces graph • Any path from all operations unknown to all known is a valid schedule • Shortest paths are minimum latency schedules Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  20. 2 0 1 000 i00 ij0 00h i0h ijh 3 All Minimum Latency Schedules • Symbolic reachable state analysis • Newly reached states are saved each cycle • Backward pruning preserves transitions used in all shortest paths Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  21. 2 0 1 000 i00 ij0 00h i0h ijh All Minimum Latency Schedules • Symbolic reachable state analysis • Newly reached states are saved each cycle • Backward pruning preserves transitions used in all shortest paths Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  22. 0 1 000 i00 ij0 00h i0h ijh All Minimum Latency Schedules • Symbolic reachable state analysis • Newly reached states are saved each cycle • Backward pruning preserves transitions used in all shortest paths Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  23. 0 000 i00 ij0 00h i0h ijh All Minimum Latency Schedules • Symbolic reachable state analysis • Newly reached states are saved each cycle • Backward pruning preserves transitions used in all shortest paths Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  24. 000 i00 ij0 00h i0h ijh All Minimum Latency Schedules • Described construction is Exact -- • Suitable heuristics are available and since they can use arbitrary subsets of the potential schedules are powerful Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  25. Resource Class Fork j2 Operation Data Dependency j1 k1 i1 h1 i2 Control Dependency Join CDFG Representation Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  26. 0 1 0 1 Control value known CDFGs: Multiple Control Paths • Guard automata differentiate control paths • Before control operation scheduled: Control value unknown • After control operation scheduled: • Guards are implemented as modified operation automata Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  27. CDFGs: Multiple Control Paths • All control paths form ensemble schedule • Possibly 2c control paths to schedule (non-looping case) • Dummy operation identifies when control path terminates • Only one termination operation • Ensemble schedule need not be causal! • Need solution for each control path (Completeness) • Need compatibility between paths whose control is not resolved (Causality) • Solution: validation algorithm • Validation is a path to path property for all control paths in ensemble schedule • Fixed Point Iteration Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  28. c i j t cij0 0ij0 0000 0i00 c000 00j0 ci00 ci0t c0j0 c0jt cijt CDFG Example • One green resource • Shortest paths • False termination Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  29. 0000 0i00 c000 00j0 ci00 0ij0 c0j0 cij0 cijt Validated CDFG Example • Validation algorithm ensures control paths don’t bifurcate before control value is known Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  30. 0000 0i00 00j0 ci00 c0j0 cij0 cijt Validated CDFG Example • Validation algorithm ensures control paths don’t bifurcate before control value is known • Pruned for all shortest paths as before Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  31. Validation Algorithm • Validation Proceeds on potential traces • Re-traverse Automata, Dynamically Modifying Transition Relation based on current available states in each time step: Allow guard computation only for states with matching histories if the guard is true or false. • Iterate until fixed point on all paths • Apply the following non-linear filter to each transition: Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  32. Selected CDFG Benchmarks Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  33. Large Benchmarks 957 Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  34. Heuristic Comparison of CPU Times Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  35. Required CPU Seconds Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  36. Construction for Looping DFG’s • Use trick: 0/1 representation of the MA could be interpreted as 2 mutually exclusive operand productions • Schedule from ~know -> known -> ~known where each 0->1 or 1->0 transition requires a resource. • Since dependencies are on operands, add new dependencies in 1 ->0 sense as well • Idea is to remove all transitions which do not have complete set of known or ~known predecessors for respective sense of operation • So -- get looping DFG automata as nearly same automata as before • preserve efficient representation • Selection of “Minimal Latency” solutions is more difficult Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  37. (n-k) A 1 0 (k+1) B B 1 0 1 0 C C C 1 0 1 0 1 0 D D D 1 0 1 0 1 0 E E E 1 0 1 0 1 0 F F 1 0 1 0 G 1 0 0 1 Resource Bound (at most 4 out of 7) Loop construction: resources • Resources: we now count both 0 -> 1 and 1 ->0 transition as requiring a resource. • Use “Tuple” BDD construction: at most k bits of n BDD • Despite exponential number of product terms, BDD complexity: O(bound * |V|) Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  38. v1 v2 v3 v4 Present State Next State 0,1,8,9 0,1 0,1,2,3,8,9,A,B 2,3 4,5,6,7,C,D,E,F 4,5,C,D 2,3,6,7,A,B,E,F 6,7,A,B 0,1,4,5,8,9,C,D 8,9 6,7,E,F E,F Example CA • State order (v1,v2,v3,v4) • Path 0,9,C,7,2,9,C,7,2,…is a valid schedule. • By construction, only 1 instance of any operator can occur in a state. Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  39. Strategy to Find Maximal Throughput • CA automata construction simple • How to find closed subset of paths guaranteeing optimal throughput • Could start from known initial state and prune slow paths as before-- but this is not optimal! • Instead: find all reachable states (without resource bounds) • Use state set to prune unreachable transitions from CA • Choose operator at random to be pinned (marked) • Propagate all states with chosen operator until it appears again in same sense • Verify closure of constructed paths by Fixed Point iteration • If set is empty -- add one clock to latency and verify again • Result is maximal closed set of paths for which optimal throughput is guaranteed Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  40. a b c d e Maximal Throughput Example • DFG above has closed 3-cycle solution (2 resources) • However- average latency is 2.5-cycles • (a,d) (b,e) (a,c) (b,d) (c,e) (a,d) … • Requires 5 states to implement optimal throughput instance • In general, it is possible that a k-cycle closed solution may exist, even if no k-state solution can be found • Current implementation finds all possible k-cycle solutions Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  41. EWF Looping Benchmarks 268 Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  42. Synthetic Benchmarks • Over 100 synthetic benchmarks tested • Sizes 50 operator, 100 operator, randomly assigned dependency chains, resources • 32% had no causal schedule • 35% had all maximum throughput schedules found in 15 minute timeout (1 minute Reachable States, 14 minute Fixed Point) • 33% Timed Out • Analysis of timeout cases: most included disconnected independent sub-graphs • Trial partitioning of the Transition Relation looks very promising on these cases (time/space reduction nearly quadratic!) Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  43. Synthetic Loop Benchmarks Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  44. Schedule Exploration: Loops • Idea: Use partial symbolic traversal to find states bounding minimal latency paths • Latency-- Identify all paths completing cycle in given number of steps • Repeatability-- Fixed Point Algorithm to eliminate all paths which cannot repeat in given latency • Validation-- Ensure all possible control paths are present for each remaining path • Optimization-- Selection of Performance Objective Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  45. Loop Cut i a j b k c l d a~ I~ b~ j~ c~ k~ d~ L~ Kernel Execution Sequence Set • Path from Loop cut to first repeating states • Represents candidates for loop kernel Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106 Loop Kernel

  46. i a j b k c l a~ i~ b~ j~ c~ K~ l~ Repeatable Kernel Execution Sequence Set • Fixed-point prunes non-repeating states • Only repeatable loop kernels remain • Paths not all same length • Average latency <= shortest Repeating Kernel Loop Cut Repeatable Loop Kernel Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  47. Validation I • Schedule Consists of bundle of compatible paths for each possible future • Not Feasible to identify all schedules • Instead, eliminate all states which do not belong to some ensemble schedule • Fragile since any further pruning requires re-validation • Double fixed point Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  48. i j b k c l i~ b~ j~ c~ k~ l~ Validation II • Path Divergence -- Control Behavior • Ensure each path is part of some complete set for each control outcome • Ensure that each set is Causal Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  49. Loop Cuts and Kernels Loop Cut • Method Covers all Conventional Loop Transformations • Sequential Loop • Loop winding • Loop Pielining Loop Kernel Loop Cut Loop Kernel Loop Cut Loop Kernel Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

  50. Results • Conventional Scheduling • 100-500x speedup over ILP • Control Scheduling: Complexity typically pseudo polynomial in number of branching variables • Cyclic Scheudling: • Reduced preamble complexity • Capacity: 200-500 operands in exact implementation • General Control Dominated Scheduling: • Implicit formulation of all forms of CDFG transformation • Exact Solutions with Millions of Control paths • Protocol Constrained Scheduling: • Exact for small instances – needs sensible pruning of domain Forrest Brewer forrest@ece.ucsb.edu UCSB CAD and Test Group ECE/UCSB Santa Barbara CA 93106

More Related