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Ch. 5 Combinational Logic Functions

Ch. 5 Combinational Logic Functions. 이 상 훈 경남대학교 전기전자공학부. 단원목차. 5.1 Decoders 5.2 Encoders 5.3 Multiplexers 5.4 Demultiplexers 5.5 Magnitude Comparators 5.6 Parity Generators and Checkers. Basic Decoder.

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Ch. 5 Combinational Logic Functions

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  1. Ch. 5 Combinational Logic Functions 이 상 훈 경남대학교 전기전자공학부

  2. 단원목차 5.1 Decoders 5.2 Encoders 5.3 Multiplexers 5.4 Demultiplexers 5.5 Magnitude Comparators 5.6 Parity Generators and Checkers

  3. Basic Decoder • Decoder : A digital circuit designed to detect the presence of a particular digital state. • Can have one output or multiple outputs. • Example : 2-Input NAND Gate detects the presence of ‘11’ on the inputs to generate a ‘0’ output.

  4. Single Gate Decoders • Uses single gates (AND/NAND) and some Inverters. • Example: 4-Input AND detects ‘1111’ on the inputs to generate a ‘1’ output. • Inputs are labeled D3,D2,D1,D0 with D3 the MSB(most significant bit) and D0 the LSB (least significant bit). • See Figure 5.1

  5. Single Gate Decoders Figure 5.1

  6. Single Gate Examples • If the inputs to a 4-Input NAND are given as !D3, !D2, !D1, D0 then the NAND detects the code 0001 (with ! = NOT). • The output is a 0 when the code 0001 is detected. • This type of decoder is used in Address Decoding for a PC System Board.(ex 5.2)

  7. Multiple Output Decoders • Decoder circuit with n inputs can activate m= 2n load circuits. • Called a n-line to m-line decoder such as a 2 to 4 or a 3 to 8 decoder. • Usually has an active low enable called !G to enable the decoder outputs.

  8. Truth Table for 3 to 8 Decoder

  9. 3 to 8 Decoder Circuit Figure 5.6

  10. Digital Simulation • Simulation : The verification of a digital design using timing diagram before programming the design in a CPLD. • Used to check the Output Response of a design to an Input Stimulus using a timing diagram. • See Figure 5.8

  11. Digital Simulation Figure 5.8

  12. MAX PLUSII Simulation • Basic Steps • 1. Enter Nodes from SNF (on Node Menu) • 2. Set End Time (File Menu) for length • 3. Set Grid Size (Options Menu) • See Fig. 5.9 ~ 5.15 • 4. Use Toolbar to set input stimulus • 5. Open Simulator Engine, Press Start

  13. Simulation Results Figure 5.21

  14. Decoder 2 to 4 VHDL Entity --Basic VHDL Entity for IO ENTITY decode1 IS PORT(D1,D0 : IN BIT; Y0,Y1,Y2,Y3 : OUT BIT); END decode1;

  15. Decoder 2 to 4 VHDLArchitecture -- Use Concurrent Signal Assignment ARCHITECTURE decoder OF decode1 IS BEGIN Y0 <= (not D1) and (not D0); Y1 <= (not D1) and (D0); Y2 <= (D1) and (not D0); Y3 <= (D1) and (D0); END decoder;

  16. VHDL Architecture • Data Flow Architecture (decoder) uses concurrent signal assignments (Boolean). • Concurrent Signals: All outputs change at the same time not sequential (order is not important) • Most common Architecture for combinational logic designs

  17. Selected Signal Assignments • Uses a VHDL Architecture construct called WITH SELECT. • Basic Format is: • WITH (signal input(s)) SELECT • signal input states are used to define the output state changes.

  18. Decoder VHDL Entity • Basic Entity for Selected Signal ENTITY decode1 IS PORT( D : IN STD_LOGIC_VECTOR(1 downto 0); Y :OUT STD_LOGIC_VECTOR(3 downto 0)); END decode1;

  19. Selected Signal Entity • In the previous slide the Entity used a STD LOGIC Array for Inputs and Outputs. • The Y :OUT STD_LOGIC_VECTOR(3 downto 0) is equal to Y3, Y2, Y1, Y0. • The STD_LOGIC Data Type is similar to BIT but has added state values such as Z, X, H, and L instead of just 0 and 1.

  20. Selected Signal Architecture • Basic Architecture ARCHITECTURE decoder OF decode1 IS BEGIN WITH (D) SELECT Y <= “0001” WHEN “00”, “0010” WHEN “01”, “0100” WHEN “10”, “1000” WHEN “11”, “0000” WHEN OTHERS; END decoder;

  21. Decoder Architecture • The Previous Architecture used a SELECT to evaluate D to determine the Output Y. • Both D and Y are defined as an Array (or bus or vector) Data Type. • The last state for WHEN OTHERS is added for the other logic states (Z, X, H, L, etc.).

  22. Seven Segment Displays I • Seven Segment Display: An array of seven independently controlled LEDs shaped like an 8 that can be used to display decimal digits. • Common Anode Display: A SS display where the anodes of all the LEDs are connected together to Vcc and a ‘0’ turns on a segment (a to g).

  23. Seven Segment Displays II • Common Cathode Display (CC): A display where all the cathodes are connected and tied to ground, a ‘1’ turns on a segment. • An LED (light emitting diode) will turn on when the anode is made positive with respect to the cathode.

  24. Seven Segment Decoder/Drivers I • Receives a BCD(Binary Coded Decimal) 4 Bit input to present a digit (0000 - 1001) 0 through 9. • Generates Outputs (a - g) for each of the display LEDs. • Requires a current limit series resistor for each segment.

  25. Seven Segment Decoder/Driver II • Decoders for a CC-SS have active high outputs while decoders for a CA-SS have active low outputs (a to g). • The outputs generated for the binary input combinations of 1010 to 1111 are don’t cares. • The decoder can be designed with VHDL or MSI Logic (7447, 7448).

  26. SS Decoder Entity • Basic Entity ENTITY bcd_7seg IS PORT( d3, d2, d1, d0 :IN BIT; a,b,c,d,e,f,g :OUT BIT); END bcd_7seg; -- Defines binary inputs d0 to d3 -- Defines SS outputs a to g

  27. SS VHDL Architecture (CA) I • Seven Segment signal declarations ARCHITECTURE seven_segment OF bcd_7seg IS SIGNAL input : BIT_VECTOR(3 downto 0); SIGNAL output : BIT_VECTOR(6 downto 0); BEGIN input <= D3 & D2 & D1 &D0 -- Uses two intermediate signals called input and output (internal no pins) -- Creates an array by using the concatenate operator (&) In this case input(3) <= D3, input(2) <= D2 etc.

  28. SS VHDL Architecture (CA) II • SS Architecture need some states WITH input SELECT output <= “0000001” WHEN “0000”, output <= “1001111” WHEN “0001”, output <= “0010010” WHEN “0010”, output <= “0000110” WHEN “0011”, output <= “1001100” WHEN “0100”, output <= “0100100” WHEN “0101”, | | | output <= “1111111” WHEN OTHERS;

  29. SS VHDL Architecture (CA) III • SS Architecture continued a <= output(6); b <= output(5); c <= output(4); d <= output(3); e <= output(2); f <= output(1); g <= output(0); END seven_segment;

  30. SS VHDL File Description • In the preceding example file a concurrent select signal assignment was used (WITH (signals) SELECT. • The intermediate output signals were mapped to the segments (a to g). • Example when Input (D3 - D0) is 0001 the decoder sets a=d=e=f=g=1, b=c=0.

  31. Ripple Blanking I • Ripple Blanking: A technique used in a multiple digit displays that suppresses leading/trailing zeros but allows internal zeros to be displayed. • Uses a RBI (active low) Input and a RBO (active low) output. • When D0 - D3 = 0000 and RBI = 0 then display is blank.

  32. Ripple Blanking II • When D0 - D3 = 0000 and RBI = 1 then display is a 0. • If RBI = 1 or D0 - D3 /= 0000 then RBO = 1. • To suppress leading zeros connect RBI of MS Digit to Gnd, and RBO to RBI of the next least significant display.

  33. Sequential Process in VHDL • A VHDL Process is a construct that encloses sequential statements that are executed when a signal in a sensitivity list changes. • Basic Format PROCESS(Sensitivity List) BEGIN Sequential Statements; END PROCESS;

  34. Ripple Blanking Process I • Basic Process added to previous file. PROCESS(nRBI, input) BEGIN IF(input = “0000” and nRBI = ‘0’) THEN output <= “1111111”; -- Suppressed 0 nRBO <= ‘0’; ELSIF(input = “0000” and nRBI = ‘1’) THEN output <= “0000001”; -- Display a 0 nRBO <= ‘1’; ELSE -- Continued on next slide

  35. Ripple Blanking Process II • This replaces some of the old file CASE input IS WHEN “0001” => output <= “1001111”; -- a 1 Displayed WHEN “0010” => output <= “0010010”; -- a 2 Displayed | | | | | WHEN Others => output <= “1111111”; -- Blank END CASE; nRBO <= ‘1’; END IF;

  36. CASE Statement • In the RB Design we replaced the Selected Signal Assignment (With Select) with a Case Statement to generate the outputs for the SS Display. • The Process Steps are evaluated in sequence first the IF statements, then the Case and so on.

  37. IF THEN ELSE • The IF THEN ELSE Statements were used for conditional testing of some inputs (the data and RBI). • IF the data is this value THEN do these statements ELSE do this. • This is a very simple statement that is used a great deal in sequential logic.

  38. Basic Encoders • Encoder: A digital circuit that generates a specific code at it’s outputs in response to one or more active inputs. • It is complementary in function to a decoder • Output codes are usually Binary or BCD. • Priority Encoder: An encoder that generates a code based on the highest priority input.

  39. Encoder 8 to 3 Truth Table • An input is Active High D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 | | | | | 1 0 0 0 0 0 0 0 1 1 1

  40. Encoder 8 to 3 Equations • In the previous truth table each line selected 0 through 7 generates it’s own binary code such as a 1 is a 001, 5 is a 101 and so on. • Boolean Equations for Outputs Q2 = D4 + D5 + D6 +D7 Q1 = D2 + D3 + D6 + D7 Q0 = D1 + D3 + D5 + D7

  41. Priority Encoder I • The standard encoder equations given in the previous slide would be in error if two inputs were active at the same time. • If D3 = D5 then Output is 111 not 101 or 011 as expected. • Add priority to the inputs so that if D3 and D5 are equal D3 is ignored and the output code is then 101.

  42. Priority Encoder II • Both types of designs are still Boolean equations and can be done in VHDL with basic concurrent logic statements. • Priority Encoder Equations Q2 = D7 + D6 + D5 + D4 Q1 = D7 + D6 + !D5!D4D3 + !D5!D4D2 Q0 = D7 + !D6D5 + !D6!D4D3 + !D6!D4!D2D1 (refer to table 5.5)

  43. Priority Encoder VHDL Architecture • Brief Architecture for 8 to 3 Priority Enc. ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR(7 downto 0); q : OUT BIT_VECTOR(2 downto 0)); END hi_pri8a ; ARCHITECTURE priorenc OF enc8to3 IS BEGIN -- concurrent signal assignments Q(2) <= D(7) OR D(6) OR D(5) OR D(4); Q(1) <= D(7) OR D(6) OR ((not D(5)) and (not D(4)) and D(3)) OR ((not D(5)) and (not D(4)) and D(2)) ; Q(0) <= -- In a similar fashion END priorenc;

  44. Another VHDL Encoder • A WHEN ELSE is similar to If-Then-Else. ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR(7 downto 0); q : OUT INTEGER RANGE 0 to 7); END hi_pri8a ; ARCHITECTURE a OF hi_pri8b IS BEGIN -- conditional signal assignments Q <= 7 WHEN D(7) = ‘1’ ELSE -- The highest-priority condition is examined first 6 WHEN D(6) = ‘1’ ELSE 5 WHEN D(5) = ‘1’ ELSE 4 WHEN D(4) = ‘1’ ELSE 3 WHEN D(3) = ‘1’ ELSE 2 WHEN D(2) = ‘1’ ELSE 1 WHEN D(1) = ‘1’ ELSE 0; END a;

  45. Another VHDL Encoder • A If-Then-Else must be used within a PROCESS statement. ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR(7 downto 0); q : OUT INTEGER RANGE 0 to 7); END hi_pri8a ; ARCHITECTURE a OF hi_pri8b IS BEGIN PROCESS (d) BEGIN IF (d(7) = ‘1’) THEN q <= 7; ELSIF (d(6) = ‘1’) THEN q <= 6; --- ELSIF (d(1) = ‘1’) THEN q <= 1; ELSE q <= 0; ENDIF; END PROCESS; END a;

  46. Simulation Results • 8-to-3 Priority Encoder(Fig. 5-31)

  47. Basic Multiplexers • Multiplexer: A digital circuit that directs one of several inputs to a single output based on the state of several select inputs. • A MUX is called a N to 1 MUX that requires M Select inputs such that N = 2M. • For example a 4 to 1 MUX requires 2 Select inputs (S1 and S0). • Fig. 5.34, 5.37

  48. 4:1 Multiplexers (Fig 5.34 & 5.37) Y = D0!S1!S0 + D1!S1S0 + D2S1!S0 + D3S1S0

  49. Multiplexer Logic • The basic Boolean expression for a 4 to 1 is • Y = D0(!S1!S0) + D1(!S1S0) + D2(S1!S0) + D3(S1S0). • This expression can be expanded to any size MUX so the VHDL architecture could use a very long concurrent Boolean statement. • Easier approach is to use the CASE Statement again.

  50. MUX 4 to 1 (case statement in a process) ARCHITECTURE mux4to1 OF mux4 IS BEGIN PROCESS(S) -- Process is sensitive to S (S1,S0) Selects BEGIN CASE S IS WHEN “00” => Y <= D(0); WHEN “01” => Y <= D(1); WHEN “10” => Y <= D(2); WHEN “11” => Y <= D(3); WHEN OTHERS => Y <= ‘0’; END CASE; END PROCESS; END mux4to1;

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