ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices

1. ECE 3110: Introduction to Digital SystemsChapter 5Combinational Logic Design Practices Programmable Logic Devices

2. Previous… • Timing Circuits • Timing diagrams • Single value delay • Min:typical:max delay specifications • Propogation delays • LOW-to-HIGH and HIGH-to-LOW delays • Worst-case delay

3. Programmable Logic Devices (PLDs) • PLDs can implement wide functions efficiently (functions with many input variables). • PLDs can implement multiple functions of different variables efficiently. • The logic in PLDs is programmable -- it can be defined by the user and programmed on the desktop • Most PLDs can be erased and reprogrammed many times.

4. PLD types • There are MANY different types of PLDs. • Densities ranges from from 10’s of gates to 100’s of thousands of gates. • We will look at PLAs(Programmabe Logic Arrays) and PALs (Programmable Array Logic devices).

5. Programmable Logic Arrays (PLAs) • Any combinational logic function can be realized as a sum of products. • Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. • n variables • AND gates have 2n inputs -- true and complement of each variable. • m outputs, driven by large OR gates • Each AND gate is programmably connected to each output’s OR gate. • p AND gates (p<<2n)

6. Example: 4x3 PLA, 6 product terms

7. Compact representation • Actually, closer to physical layout (“wired logic”).

8. Some product terms

9. PLA Electrical Design • See Section 5.3.5 -- wired-AND logic

10. Programmable Array Logic (PALs) • PLAs • Both AND and OR arrays are programmable • Product terms can be shared by OR gates • PALs ==> fixed OR array • Each AND gate is permanently connected to a certain OR gate. • AND arrays are programmable, while OR arrays are not. • Product terms cannot be shared by OR gates

11. Understanding the Diagram D J P Vertical Lines indicate a product term. Horizontal lines provide True and Complemented forms of external inputs. Even though a product term looks like it has only one input, it actually has 2 * N inputs, where N is the number of external inputs.

12. Product Term B B’A A’ C C’ D D’I I’ J J’ E E’ F F’ K K’GG’H H’ This looks like an AND gate with one input. Is actually: B B’ A A’ C C’ H H’ Only drawn with a single line to save space.

13. Fuse Points D J P A cross over of a Vertical input line and a horizontal product term line is a FUSE LOCATION. When the PAL is in its blank or erased state, all FUSES are connected. This means that each product term implements the equation: ( A A’ B B’ C C’……. KK’) will be ‘0’! This means that the output will be high!

14. PAL Programming D J P To program, will want to BLOW most of the fuses (break the vertical/horizontal crossover connection). To indicate a logic function, will use a ‘ X ‘ over a fuse that I want to KEEP INTACT. Will mark Intact fuse location. When a fuse is blown, that product term input acts as a ‘1’ so that the input no longer effects the product term.

15. P’ = D + J’ D J P When implementing an equation, sometimes will not want to use all available product terms. If ALL fuses along product term are left intact, then product term value will be ‘0’ and will not affect equation. Mark unused PT’s by placing an X over them. Note that P’ must be implemented!

16. Example Product Term AC’H’ B B’A A’ C C’ D D’I I’ J J’ E E’ F F’ K K’GG’H H’ The connections will be: 1 Fuse blown 1 Fuse blown A Fuse intact Fuse blown 1 1 Fuse blown Fuse intact C’ 1 Fuse blown H’ Fuse intact Actually, fuses are not ‘blown’ in eraseable PLDs - the connection is broken in a non-destructive way for eraseable PLDs.

17. Another Example A G B H C I D J P P’ = A’BGH’ + CD’ + HIJ + BG’H

18. 10 primary inputs • 8 outputs, with 7 ANDs per output • 1 AND for 3-state enable • 6 outputs available as inputs • more inputs, at expense of outputs • two-pass logic, helper terms • Note inversion on outputs • output is complement of sum-of-products • newer PALs have selectable inversion

19. Next… • HW #9 • Building blocks • Decoders • Encoders • Reading Wakerly CH-5.4-5.5