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Test and Characterization of a Variable-Capacity Multilevel DRAM

Test and Characterization of a Variable-Capacity Multilevel DRAM. VLSI Test Symposium May 1 - 5, 2005 John Koob , S. Ung, A. Rao, D. Leder, C. Joly, K. Breen, T. Brandon, M. Hume, B. Cockburn, D. Elliott VLSI Design Laboratory University of Alberta Edmonton, Canada. 17/2/2005 v3.2.

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Test and Characterization of a Variable-Capacity Multilevel DRAM

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  1. Test and Characterization of a Variable-Capacity Multilevel DRAM VLSI Test Symposium May 1 - 5, 2005 John Koob,S. Ung, A. Rao, D. Leder, C. Joly, K. Breen, T. Brandon, M. Hume, B. Cockburn, D. Elliott VLSI Design Laboratory University of Alberta Edmonton, Canada 17/2/2005 v3.2

  2. Outline • Motivation • MLDRAM Overview • MLDRAM Fault Model • Basic Functional Test • Cell Voltage Drift Test • Multilevel March Test • Bitline Coupling Test • Cell Plate Bump Test

  3. Motivation Source: Computer Architecture: A Quantitative Approach, Hennessy and Patterson, 2003

  4. DRAM vs. MLDRAM

  5. Possible Storage Encoding Scheme • 6 signal levels • 5 binary bits are encoded from 2 cells • 2.5 bits/cell on average

  6. Read Operation in 4-Level MLDRAM Reference Generation (1) Reference Generation (2) Access Data & Reference Cells Copy Signal and Parallel Sense Restore Accessed Data Cells

  7. Multilevel DRAM Fault Model • Fault types: • SAF0/SAF1 - involves single code bit • SAF-random - several causes • SCF - interdependence among code bits • data retention fault • degraded noise margins Source: Redeker, et al, “Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM,” MTDT, July 2002, pp. 117-122.

  8. Basic Functional Test Results 1. Write data level to base cell B 2. Write contrasting levels to N1 & N2 3. Read cell B and verify

  9. Cell Voltage Drift Test 1. Write highest signal level to a set of cells 2. Wait for a predefined drift time 3. Test drift using page-mode read Graphical analysis using drift bitmaps: • new way to monitor cell drift • detects stuck bits, bitlines and wordlines • detects sense amplifier offsets

  10. Cell Drift Test Results Predominant Thermometer Code

  11. Multilevel March Test • A 12n march test for six-level MLDRAM (using 5-digit thermometer codes):  {w00000}  {r00000, w00001}  {r00001, w00011}  {r00011, w00111}  {r00111, w01111}  {r01111, w11111}  {r11111} • 100% cell yields (four-level, 55-fF cell)

  12. Inter-Bitline Coupling Test

  13. Bump Test • Nominal curve is centered between two references • DUT circuit to control back-bias

  14. Multilevel Bump Test • Curves are from bump tests for each level • Nominal references: 0.3V, 0.9V, 1.5V • Lowest noise margin: sensing 111

  15. Conclusions • MLDRAM success depends on effective characterization and testing • 100% cell yield for 55-fF cells in 4-level mode • Future test chips need a DRAM process • Industrial partners are welcome • Could fix the DRAM-disk access time gap by: • Increasing capacity vs. DRAMs • Sacrificing performance to improve cost per bit • Revisiting theextended storagehierarchy stage

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