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Daniel D. Gajski, Fellow, IEEE, Frank Vahid, Member, IEEE, Sanjiv Narayan, and Jie Gong

SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Desgin. Daniel D. Gajski, Fellow, IEEE, Frank Vahid, Member, IEEE, Sanjiv Narayan, and Jie Gong IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. 6, NO. 1, MARCH 1998 Presented by: Jun Zhu. Outline.

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Daniel D. Gajski, Fellow, IEEE, Frank Vahid, Member, IEEE, Sanjiv Narayan, and Jie Gong

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  1. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Desgin Daniel D. Gajski, Fellow, IEEE, Frank Vahid, Member, IEEE, Sanjiv Narayan, and Jie Gong IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. 6, NO. 1, MARCH 1998 Presented by: Jun Zhu

  2. Outline • Intruction • SyecSyn environment(support SER paradigm) • Experiments • Compared with related works & Conclusions

  3. Part1 Intruction Three distinct tasks design problem • Specify system functionality and constraints • Explore various system-level design alternatives • Refine the original specification However, these three steps are not satisfying now • Lack of early simulation=>Simultable specification • Lack of automated tools=>Automated tool in exploration • Lack of good document=>Refined implementation description

  4. Specification Capture Exploration Specification Refinement After SER, we perform SW/HW design and SW/HW implementation. Fig1 SER approach to System Design

  5. Two key features of SpecSyn: System-level description could be easily understood, and extensively used. It is a general tool, intended to support various implementation component technologies, and is extensible. Fig2 The SpecSyn system-design environment

  6. Part2.1 Specification Capture Models and Languages • Program-state machine (PSM) model • SpecCharts language

  7. Internal Representation • CDFG is too fined-grained • Representing dependence causes duplicated objects We develop a representation that focuses on representing accesses among objects.

  8. SLIF-AG is in directed graph Graph node represents a behavior (process/procedure) or a variable. A channel/edge represents an access/procedure call, which includes variables also. Fig3 Specification-level-intermediate format Access Graph for a Fuzzy Logic Controller

  9. Part2.2 Exploration Create a system-level design of the interconnected components: • Allocation • Partitioning • Estimaiton • Transformation

  10. a) Allocation • To add possible components to the design • Each component is characterized in a library by its constraints, and by a technology file

  11. b) Partitioning There are three types of functional objects • Variables are assigned to memory • Behaviors are assigned to processor • Channels are assigned to buses

  12. b) Partitioning – Cost Function • Partitioning heuristics are evaluated by Cost Function • To control the relative weights of various metrics in Cost Function to see whether a partition meets all constraints – obtain zero cost Fig4 Cost Function

  13. c) Estimation To determined whether a particular system-level design satisfies constraints, and to compare alternative designs. There are two levels • Pre-estimation • Online-estimation

  14. c) Estimation - Pre-estimation • Pre-estimation occurs only once at the beginning of exploration • each function is annotated with information when compiled to a particular processor

  15. c) Estimation – Online-estimation • It occurs hundreds or thousands of times during manual or automated exploration. SpecSyn estimation model • Performance • Hardware size • Software size

  16. Fig5 Subtasks in exploration

  17. d) Transformation • Inner loop – SLIF transformations occur along with allocation, partitioning and online estimation, which might be applied thousands of times. • Outer loop – Specification transformations is followed by rebuilding of the SLIF and reannotation.

  18. Part2.3 Refinement Generate a new specification for each system component after a suitable allocation and partition. • Interfacing - determines the buswidth and the protocol • Memories – implementation of variables • Arbitration – when there is a resource contention • Generation – generate the refined specification • Validation – simulate the refined specification

  19. Part3 Experiments • The results were generated automatically, SpecSyn aids the designer to focus on promising points. • The result obtained matched with those obtained by an engineer who did a manual partition. Fig6 Results for FLC for 35 different allocations

  20. Part4 Compared with related works & Conclusions • SpecSyn outputs software at the algorithmic level, which is coarse-grained. • It supports a variety of system architectures. • SpecSyn uses a two-level estimation method ( pre-estimation and online-estimaiton) We expect that this paradigm and tool will result in a 100h-design cycle, which is nearly a ten times reduction in design time from the six months required to design manually.

  21. Thank you!

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