VHDL Slicer Design and Implementation of a Slicer for VHDL Programs.

1. VHDL SlicerDesign and Implementation of a Slicer for VHDL Programs. • Program Slicing : Analysis technique of extracting parts of a given program, relevant to the aspects being analyzed (the slicing criterion). E.g. slicing criterion : <line number, variable> slice : subset of the statements in the program that affect the variable at that line number. • Applications • Debugging • Component Extraction • Maintenance • State Space Reduction in Formal Verification

2. read(n); • i:=1; • sum := 0; • product :=1; • while i<=n do { • sum :=sum +i; • product:=product * i; • i := i +1; } • write(sum); • write(product); • Slicing criterion: <line number, variable> • read(n); • i:=1; • product :=1; • while i<=n do { • product:=product * i; • i := i +1; } • write(product); slice wrt <10,product>;

3. Reduced VHDL Program "Slice" VHDL Program VHDL Slicer Output Signal "Slicing Criterion" • Slicing Criterion for VHDL Programs : An output signal (s). • Requirements : For any input vector the behaviour of the slice, w.r.t. signal s should be identical to that of the original program.

4. cfg_gen dflow_analyzer VAUL cdg_gen code_gen reachability VHDL Program CFG AST DDS CDS PDG Entity1.PDG Sliced VHDL Program Entity2.PDG Reduced SDG SDG Slicing criterion EntityN.PDG VAUL : VHDL Analyzer and Utility Library AST: Abstract Syntax Tree PDG: Program Dependence Graph CFG : Control Flow Graph SDG : System Dependence Graph DDS: Data Dependence SubGraph CDS: Control Dependence SubGraph

5. Entity adder isArchitecture rtl of adder is port(a,b,cin : in bit; s<= a xor b; sum,cout : out bit;) sum<= s xor cin; End adder cout <= (a and b) or (s and cin); end rtl; Program Dependence Graph :