Implementing RISC Multi Core Processor Using HLS Language - BLUESPEC

1. Semesterial Winter 2013 Implementing RISC Multi Core Processor Using HLS Language - BLUESPEC Liam Wigdor Instructor MonyOrbach Shirel Josef

2. Motivation Project Goals Solution Algorithm Project Diagram Development Evnironment Project Gantt AGENDA

3. Motivation • The future of single core is gloomy • Multi cores can be used for parallel computing • Multi cores may be used as specific accelerators as well as general purpose core. • Multi cores may be used to overcome the Dark Silicon problem as different cores can have different properties.

4. Project Goals • Main Goal: • Implementing RISC multi core processor using BlueSpec • Derived Goals: • Learning the BlueSpecprinciples, syntax and working environment. • Understanding and usingRISC processor to implement multi core processor. • Validate design by using simple bench mark programs and evaluating performance to single core.

5. Multi Core architectures • GPU initially used the “multi core” concept • Memory management performed by memory controller that allocates memory chunks to the “cores” (execution units)

6. However, we will use: Solution Algorithm: • In order to improve single core performance we will implement dual core processor with scalability. Steps: First, we will implement processor with 2 cores sharing data memory.Second, we will implement 2 cores with private caches sharing data memory.

7. Design Block Diagram Shared memory and each core has private cache Shared memory without cache Core 1 Core 2 Core 1 Core 2 Cache 1 Cache 2 Shared memory Shared memory

8. Development Evnironment • SCE-MI – Provides communications protocols between hardware and software. • Xilinx Tools

9. Why BlueSpec? • Atomic rules and interface – allow higher level abstraction • Synthesizable Verilog RTL • 100% architectural transparency • Easy to understand code

10. What is SCE-MI? • Multiple communication channel that Allow software models to connect to structural models • Provides interface between the software and the hardware

11. Xilinx Tools • Xilinx ML505 Evaluation Platform • Synthesis – from compiling verilog to gate level implementation

12. Project Gantt 2013-2014 27/10 3/11 10/11 17/11 24/11 1/12 8/12 15/12 22/12 29/12 • Learning BlueSpec • Architecture Design • Learning single core implementation(without cache) • BlueSpec oriented multi-core design (no cache) • Cache implement if possbile • CDR • prep