Lecture 4: Load/Store Architectures

1. Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier

2. LADIES AND TIGERS

3. The Lady and the Tiger • Two doors containing either Ladies or Tigers

4. The Lady and the Tiger • You will be shown two doors, to two rooms. • Each could contain either a lady or a tiger… • It could be that both rooms contain a lady, or that both rooms contain a tiger! • You will need to reason carefully and logically to survive! • Each question, pick a door, or decide not to open a door. • You score one point for picking a lady, or for refusing to pick if both doors contain tigers. • Three points available for your homework/projects grade today • If you answer wrong, you may write a short paper describing what you did wrong, and how to find the right answer, due next class.

5. The Lady and the Tiger • Form up into groups • On a sheet of paper, list the first and last names of each student in the group, and pick a team name • Discuss your answers, and record them • Each group will then give their answers to the class

6. The Lady and the Tiger Q1 One of these is true… The other is false… In one of these rooms there is a lady, and in one of these rooms there is a tiger. In this room, there is a lady, and in the other room there is a tiger.

7. The Lady and the Tiger Q1 One of these is true… The other is false…

8. The Lady and the Tiger Q2 Either both signs are false… Or both are true… A tiger is in the other room… At least one of these rooms contains a lady

9. The Lady and the Tiger Q2 Either both signs are false… Or both are true…

10. The Lady and the Tiger Q3 Either both signs are false… Or both are true… An lady is in the other room. Either a tiger is in this room, or a lady is in the other room.

11. The Lady and the Tiger Q3 Either both signs are false… Or both are true…

12. What does this have to do with CS?

13. CS and CE • What are the disciplines? • Computer Engineering? • Computer Science?

14. What it isn’t • "What would we like our children- the general public of the future—to learn about computer science in schools? We need to do away with the myth that computer science is about computers. Computer science is no more about computers than astronomy is about telescopes, biology is about microscopes or chemistry is about beakers and test tubes. Science is not about tools, it is about how we use them and what we find out when we do." -- Ian Parberry

15. What it isn’t • A confusion of even longer standing came from the fact that the unprepared included the electronic engineers that were supposed to design, build, and maintain the machines. The job was actually beyond the electronic technology of the day, and, as a result, the question of how to get and keep the physical equipment more or less in working condition became in the early days the all-overriding concern. As a result, the topic became —primarily in the USA— prematurely known as "computer science" —which, actually is like referring to surgery as "knife science"— and it was firmly implanted in people's minds that computing science is about machines and their peripheral equipment. -- Edsger Dijkstra

16. What it really is • Computer science is the study of the theoretical foundations of information and computation and of practical techniques for their implementation and application in computer systems. Computer scientists invent algorithmic processes that create, describe, and transform information and formulate suitable abstractions to model complex systems. • Computer engineering is the process of analyzing, designing, and integrating the hardware and software systems needed for information processing or computation. Computer engineers are saddled with the difficult tasks of modeling, designing, and analyzing cyberphysical systems which solve interdisciplinary problems in a wide variety of domains.

17. BASIC LOAD STORE

18. ARMv6 • Remember! • RISC architecture • Load/Store architecture

19. RISC Load/Store Architecture Memory Processor Load Store Registers Add Cmp Etc

20. Loading and Storing • ARM, MIPS, and other Load/Store Architectures • Do not support processing data in memory • Must first move data into registers before processing. • Sound inefficient? • In practice it isn’t! • Memory is slow, registers are fast!

21. Loading and Storing Memory • The Load/Store architecture paradigm • LOAD data values you need from memory into registers • Process data in registers • STORE the results from the registers into memory Processor Load Store Registers Add Cmp Etc

22. Single register data transfer • STR • store a word from a register STR r0, [r1] Store r0 to the location pointed to by r1 LDR r0, [r1] Load the contents pointed to by r1 into r0

23. Single register data transfer • LDR • load a word from memory into a register LDR r0, [r1] Load the contents pointed to by r1 into r0

24. Offsets • Our offset can be • An unsigned 12bit immediate value • A register • Offset can be • Added (default) • Subtracted (prefix with a ‘-’)

25. Offsets • Can be done: • Prefix: str r0, [r1, r2] Store r0 to [r1+r2] • Prefix, increment: str r0, [r1, r2]! Store r0 to [r1+r2] r1 = r1 + r2 • Postfix: str r0, [r1], r2 Store r0 to [r1] r1 = r1 + r2

26. Load/Store with Offset Prefix

27. Load/Store with Offset Postfix

28. A basic example int a[4]; a[3] = a[0] + a[1] + a[2]

29. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] Let’s say r0 contains the BASE address ofthe array a[] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 ?? r1 ?? r2 ?? r3 ?? r4 ?? … r15

30. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x00 r2 ?? r3 ?? r4 ?? … r15

31. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x00 r2 x00 r3 ?? r4 ?? … r15

32. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x00 r2 x00 r3 x05 r4 ?? … r15

33. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x00 r2 x05 r3 x05 r4 ?? … r15

34. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x01 r2 x05 r3 x05 r4 ?? … r15

35. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x01 r2 x05 r3 x02 r4 ?? … r15

36. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x01 r2 x07 r3 x02 r4 ?? … r15

37. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+2] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x02 r2 x07 r3 x02 r4 ?? … r15

38. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+2] ldr r3, [r0, r1] ;r3 = a[0+2] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x02 r2 x07 r3 x03 r4 ?? … r15

39. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+2] ldr r3, [r0, r1] ;r3 = a[0+2] add r2, r2, r3 ;r2 = r2 + r3 MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x02 r2 x0A r3 x03 r4 ?? … r15

40. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+2] ldr r3, [r0, r1] ;r3 = a[0+2] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Increment to a[0+3] MEM 0x0 x05 0x1 x02 0x2 x03 0x3 ?? REG r0 x00 r1 x03 r2 x0A r3 x03 r4 ?? … r15

41. A basic example int a[4]; a[3] = a[0] + a[1] + a[2] mov r1, #0 ;Go for a[0+0] mov r2, #0 ;Initialize sum to 0 ldr r3, [r0, r1] ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0, r1] ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+2] ldr r3, [r0, r1] ;r3 = a[0+2] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Increment to a[0+3] str r2, [r0, r1] ;a[0+3] = r2 MEM 0x0 x05 0x1 x02 0x2 x03 0x3 x0A REG r0 x00 r1 x03 r2 x0A r3 x03 r4 ?? … r15

42. Improving Performance! From 12 instructions to 9 instructions, a 25% reduction in instruction count! int a[4]; a[3] = a[0] + a[1] + a[2] movr1, #0 ;Go for a[0+0] movr2, #1 ;Initialize sum to 0 ldr r3, [r0], r1 ;r3 = a[0+0] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+1] ldr r3, [r0], r1 ;r3 = a[0+1] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Go for a[0+2] ldr r3, [r0], r1 ;r3 = a[0+2] add r2, r2, r3 ;r2 = r2 + r3 add r1, r1, #1 ;Increment to a[0+3] str r2, [r0] ;a[0+3] = r2 MEM 0x0 x05 0x1 x02 0x2 x03 0x3 x0A REG r0 x00 r1 x03 r2 x0A r3 x03 r4 ?? … r15

43. Going further, Block Data Transfer • LDM/STM • Load/Store Multiple • Allow between 1 and 16 registers to be transferred to or from memory.

44. Going further, Block Data Transfer • LDM/STM • Load/Store Multiple • Allow between 1 and 16 registers to be transferred to or from memory. More on this later

45. BASIC DATA PROCESSING

46. Architecture of ARM

47. Data Processing • Basic data processing instructions Operand 1 Register Operand 2 Destination Register

48. Data Processing • Basic data processing instructions ADD Rd = Rn + Operand2 SUB Rd = Rn – Operand2 RSB Rd = Operand2 – Rn

49. Data Processing • Basic data processing instructions ADD Rd = Rn + Operand2 SUB Rd = Rn – Operand2 RSB Rd = Operand2 – Rn MOV Rd = Operand2 MVN Rd = -Operand2 Operand2 is 12-bits long, and can be an immediate, or a register. How does the ARM know?

50. Operand2 is Versatile! • Immediate value • An 8-bit constant • Register • How many bits to address our registers r0 – r15?