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USB2.0 Host Controller

May 17, 2000. 2. USB2.0 Host Controller. John S. HowardStaff Engineer Intel Architecture LabsIntel Corporation. May 17, 2000. 3. Agenda. Project OverviewKey Features OverviewUSB 2.0 Host Controller ArchitectureHigh-Speed Host ControllerInterface ArchitectureInterface Data Structure Overview/BenefitsPower ManagementHost Controller Compliance ProgramSummary.

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USB2.0 Host Controller

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    2. May 17, 2000 2 USB2.0 Host Controller John S. Howard Staff Engineer Intel Architecture Labs Intel Corporation

    3. May 17, 2000 3 Agenda Project Overview Key Features Overview USB 2.0 Host Controller Architecture High-Speed Host Controller Interface Architecture Interface Data Structure Overview/Benefits Power Management Host Controller Compliance Program Summary

    4. May 17, 2000 4 Project Overview Enhanced Host Controller Specification for USB Defines the register (hardware/software) interface for a USB 2.0 capable host controller Revision 0.95 will be the first public release License agreement provides reciprocal royalty free license to manufacture compliant discrete USB 2.0 host controllers based on this specification

    5. May 17, 2000 5 Project Overview Revision 1.0 is the final specification License agreement provides reciprocal royalty free license to manufacture compliant USB 2.0 host controllers based on this specification Intel developed specification with contributions so far from NEC, Lucent, Philips, Compaq and Microsoft Licensees can also contribute to specification

    6. May 17, 2000 6 Project Overview Specification Development methodology Developed in parallel with USB 2.0 core specification Low-risk approach Leverage existing USB 1.1 HC implementations and knowledge base Provide solutions to well-known USB host controller problems Focus on reasonable hardware/software complexity tradeoffs Validate features whenever possible Built prototype driver and host controller in parallel with specification Host Controller Compliance Program Ensures host controllers are compliant to the specification

    7. May 17, 2000 7 USB 2.0 Host Controller Architecture Multi-function Controller delivers 3 port speeds Simplifies High-speed Host Controller Optimize for high-speed functionality Reuses USB 1.1 Host Controller Designs (drop-in) Allows port availability independent of presence of high-speed capable software

    8. May 17, 2000 8 USB 2.0 Host Controller Architecture: Port Routing Rules Ports owned by Companion controllers when HS HC software is absent When HS HC Software is present, it “configures” High-Speed HC then: Retains ownership for high-speed devices Releases individual port ownership if attached device is not high speed Routing Logic signals a disconnect on HS HC and a connect on Companion HC Ownership returns to HS HC on a disconnect event

    9. May 17, 2000 9 High-Speed Host Controller Interface Architecture Three-part Interface PCI Space Register Space Shared Memory Work Interface PCI Configuration Registers PCI Class Codes Memory space base address for register space Power Management Interface

    10. May 17, 2000 10 High-Speed Host Controller Interface Architecture Memory-based I/O Registers Capability Registers Implementation-specific, read-only parameters for driver Operational Registers Host controller management List Management Port control registers

    11. May 17, 2000 11 High-Speed Host Controller Interface Architecture Shared Memory Work Lists Two schedule Lists (periodic, asynchronous) Queuing data structures Used for transfer types guarantee delivery Different data structures used for isochronous Different data structures for high- and full-speed Optimized for streaming isochronous data No support for retries

    12. May 17, 2000 12 High-Speed Host Controller Interface Architecture (Overview)

    13. May 17, 2000 13 Shared Memory Work Lists Queuing Data Structure Queues are used for ALL Non-Isochronous transfers 1 queue per endpoint Each queue element (transaction descriptor) describes a buffer I.e. 1 to many transactions Up to 20 Kbytes per transaction descriptor 16Kbytes with worst-case buffer alignment No Hardware/software sync required to add work to a queue Architecture optimized to provide efficient memory accesses Block, burst accesses Reduced average number of memory accesses to start transaction

    14. May 17, 2000 14 Shared Memory Work Lists Queuing Data Structure (Ex.)

    15. May 17, 2000 15 Shared Memory Work Lists Isochronous Data Structures Used only in periodic list Time-oriented data structure “Frame number” encoded in topology of list Position of work item in periodic list determines when it will be “seen” and executed by the host controller No hardware (micro)-frame arithmetic required Different data structures for high-speed and low-speed High-speed data structure optimized for large transfers Full-speed data structure optimized for split-transaction support

    16. May 17, 2000 16 Shared Memory Work Lists Hardware Scatter/Gather All transfer data structures are scatter/gather capable Simple hardware implementation No pointer arithmetic required Simple concatenation of page pointer to page offset to generate buffer address Software initializes page offset, hardware manages page pointers and page offset based on transfer progress

    17. May 17, 2000 17 Power Management High-speed controller power management USB port power management PCI Bus Power Management Interface Provides per/port capabilities for managing bus power as defined in USB specification Support defined for PCI Advanced Power management interface Compliant with PCI Bus Power Management Interface Specification, Revision 1.1

    18. May 17, 2000 18 USB 2.0 Host Controller Compliance Program Compliance testing includes Standard USB 2.0 Compliance tests Standard USB 2.0 Electrical tests Host controller-specific Interface Functional Testing Availability HC compliance test will be available from Intel Method of distribution (to be defined) Alpha-level tools available in Q3 2000 Beta-level tools available in Q1 2001 Production release available with release of 1.0 host controller specification

    19. May 17, 2000 19 USB 2.0 Host Controller Compliance Program HC-specific compliance software under development at Intel Special compliance devices (high-speed and full/low speed) Special-purpose application and driver for controlled testing and analysis Interface Functional Testing Device Interoperability USB 2.0 protocol and transfer extensions System Interaction Etcetera, …

    20. May 17, 2000 20 Summary Low-risk Introduction All ports are HS/FS/LS Capable Legacy (non-high-speed aware) software just works Re-use of 1.1 controllers simplifies high-speed controller Interface optimized for good memory accesses efficiency Reasonable tradeoff of hardware/software complexity

    21. May 17, 2000 21 Summary PCI power management compliant Host controller compliance program Revision 0.95 for discrete HC Q3 2000 Gating item is validation of 2 discrete host controllers Revision 1.0 in 2001 Gating item is validation of integrated host controller

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