Simulation uses the file as data object: Input a file in test bench for simulation

1. Simulation uses the file as data object: Input a file in test bench for simulation Output a file as the simulation result Print an info(warning, error) during the simulation A VHDL file is a class of object used to store data. Like other object, it must include file-type definition. The file type declaration syntax: Type file_type is file of element_type; Example: Type integer_file is file of integer; Compare with other type declarations: Type state_type is (s0, s1); Subtype sub_integer is integer range 1 to 31

2. File type declaration --file type that can store ASCII data, readable text. --file type that can store sequence of integers, not readable Signal c_state, n_state: state_type; External file name File operating mode A file declaration creates one (or more) file objects of a given file type. We can declare a file within Architecture, process, package, and subprograms.

3. optional Predefined procedure OPEN_OK STATUS_ERROR(already opened) NAME_ERROR(file not found) MODE_ERROR(file can’t be opened) Predefined procedure, return values:

4. Procedure WRITE(file filename: FILE_TYPE; value: in type); It implicitly declared a file type and operation.

5. Predefined procedure

6. Write all contents of buf into outfile T h e F i r s t Buf(pointer)

8. Parameter of the procedure call

9. Function call and return Boolean value Next; -- only can used in loop, jump to end of loop End loop;

16. 48 If data bus = 32 bits and control signals = 16 bits, then total test vector needed = 2 to cover all possible test combinations.

18. TEST Manufacture Test set (ATE, Automatic Test Equipment) VHDL testbench

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