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A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. Jaewoong Sim Gabriel H. Loh Hyesoon Kim Mike O’Connor Mithuna Thottethodi. A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch.

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A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

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  1. A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch JaewoongSim Gabriel H. LohHyesoon Kim Mike O’Connor MithunaThottethodi

  2. A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch • Problems: Inefficiencies on current DRAM cache approach • Multi-MB/High-latency cache line tracking structure (MissMap) • Under-utilized aggregate system bandwidth • Solutions: Use speculative techniques • Replace MissMap with a low-cost Hit-Miss Predictor (HMP) • Dynamically steer hit requests either to DRAM$ or off-chip DRAM (SBD) • Maintain a mostly-clean DRAM cache via Dirty Region Tracker (DiRT) • Results: Make DRAM cache approach more practical • 20.3% faster than no DRAM cache (15.4% over the state-of-the-art) • Removed 4MB storagerequirement (employable in commercial products) New Approach: Region-Based Prediction! + TAGE Predictor-like Structure! = Less than 1KB Storage!! Provide the cache line existence info(hit or miss) Row Decoder 29 data blocks 3 tag blocks 4MB size for 1GB DRAM$!!  20+ cycles access latency!! … 2KB DRAM ROW New Approach: Hybrid Region-Based WT/WB policy for DRAM$! Always send hit requests to DRAM$? Sense Amplifier MissMap DRAM Bank Off-chip BW is under-utilized! Req. Buffer Stacked DRAM$ Another Hit Request Req. Buffer Off-chip DRAM

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